Hybrid Logical Clock ·
(l, c) preserves causality
un
seel
.com · 48-bit ms + 16-bit counter · Kulkarni 2014
Nodes
3
Max HLC
(0, 0)
Stage
three nodes, skewed wall clocks
Wall clock (pt)
Logical counter (c)
Receive — max + 1
Causal HLC chain
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.com · Hybrid Logical Clock