Electrical
Binary Adder Circuit
Half-adder and full-adder — the arithmetic core of every CPU
A binary adder computes sums of binary digits using logic gates. The half-adder adds two bits producing sum and carry. The full-adder adds three bits — two operands plus carry-in — and is chained to build multi-bit adders. Ripple-carry adders cascade full-adders sequentially. Carry-lookahead adders parallelize carry computation for speed. Adders sit at the heart of every CPU's arithmetic logic unit (ALU). Subtraction uses two's complement. Multiplication and division decompose into repeated additions and shifts.
- Half-adder2 inputs, sum + carry, XOR + AND
- Full-adder3 inputs (A, B, Cin), sum + carry-out
- Ripple-carryO(N) delay through carry chain
- LookaheadO(log N) delay, more gates
- Two's complementSubtraction via negation + add
- ApplicationALU, address calculation, counters
Interactive visualization
Press play, or step through manually. The visualization is yours to drive — try it before reading on.
Watch the 60-second explainer
A condensed visual walkthrough — narrated, captioned, under a minute.
Why adders matter
- Arithmetic logic units. Every ALU adds.
- Address calculation. Pointer arithmetic in CPUs.
- Counters. Increment registers, timers, program counters.
- DSP. Multiply-accumulate at the heart of filters and FFTs.
- Cryptography. Modular arithmetic, hash functions.
- Graphics. Pixel coordinate math, blending.
- Education. Canonical example of combinational logic.
Common misconceptions
- Adders are simple. Real adders use lookahead, carry-skip, prefix trees.
- Speed scales with bits. Without lookahead, doubling width doubles delay.
- Subtraction needs separate hardware. Two's complement reuses the adder.
- Overflow is ignored. Flags are critical for correct signed arithmetic.
- One adder fits all. Floating-point, BCD, and saturating adders differ.
- Carry-lookahead is free. Gate count and routing complexity scale.
Frequently asked questions
How does a half-adder work?
Two single-bit inputs A and B produce a sum bit S = A XOR B and a carry bit C = A AND B. When A=1 and B=1, the sum is 0 with carry 1 (binary 10). The half-adder cannot accept a carry from a previous stage, so it only suits the lowest bit of a ripple chain.
What's a full-adder?
Three inputs — A, B, and carry-in — produce a sum and carry-out. Sum = A XOR B XOR Cin. Carry-out = (A AND B) OR (Cin AND (A XOR B)). Internally it's two half-adders plus an OR gate. Cascading full-adders bit-by-bit produces an N-bit ripple-carry adder.
What's ripple-carry?
N full-adders chained so each carry-out feeds the next stage's carry-in. Simple, area-efficient, but slow — the worst-case delay equals N gate delays as the carry propagates through every stage. A 64-bit ripple adder is far too slow for modern CPU clock speeds, so faster architectures dominate.
What's carry-lookahead?
Computes whether each bit position will generate a carry (G = A AND B) or propagate one (P = A XOR B). Carries are derived from these signals in parallel using boolean expressions, collapsing the O(N) delay to O(log N). Tradeoff: many more gates and complex routing. Used in production ALUs.
How is subtraction done?
Two's complement. To compute A − B, invert all bits of B, add 1, then add A. The same adder hardware handles both add and subtract — a control bit XORs B and feeds 1 into the carry-in. This unification of addition and subtraction was the key insight that simplified early computer design.
What about overflow?
When the sum exceeds the representable range, the result wraps. Unsigned overflow is detected by the carry-out of the most significant bit. Signed overflow uses two's complement and is detected when the carry-in and carry-out of the MSB differ. CPUs expose overflow flags so software can react.
How is multiplication built?
An array of adders. Each partial product (one operand AND a shifted bit of the other) is summed by a tree of carry-save adders. Booth encoding reduces partial products. Modern CPUs perform 64-bit multiplies in 3–5 cycles using highly optimized adder trees. Floating-point multipliers add normalization and rounding stages.