Buck Converter

Why chop a perfectly good DC voltage?

You have a 12 V battery and a chip that wants 3.3 V at 5 A. The chip is going to consume 3.3 × 5 = 16.5 W either way. The question is how much heat you generate getting the power there.

The lazy answer is a linear regulator — a transistor that drops the surplus 8.7 V as resistance. Output power 16.5 W, input power 12 × 5 = 60 W, efficiency 27.5%. The other 43.5 W comes out as heat in the regulator's tab. You need a big heatsink, the battery runs flat in a third the time, and the regulator itself is the warmest thing in the box.

A buck converter takes a fundamentally different bet. Don't drop the voltage — chop it. Switch a transistor on and off 500 000 times a second, then average the resulting square wave with an inductor and capacitor. Spend 27.5% of each cycle connected to 12 V and 72.5% disconnected, and the time-average voltage is 3.3 V. The transistor is either fully on (low resistance, low loss) or fully off (no current, no loss). The inductor and capacitor have copper and dielectric losses but no fundamental thermodynamic dissipation. Efficiency: 92–96%, depending on parts. The same battery now runs three to four times as long, and the regulator stays cool.

That is the entire reason switching regulators exist. They convert at fixed efficiency regardless of voltage step, while linear regulators waste the difference. Anywhere a power rail steps down by more than a volt or two, a buck converter is the right answer.

The four-component topology

A textbook buck converter has four power components plus a load:

       SW                        L
   V_in ──/──┬──────────────UUUU───────┬─── V_out
             │                          │
             ▽ D                        ═ C    ⏚ load
             │                          │
             └──────────────────────────┴── GND

   SW = high-side switch (MOSFET)
   D  = freewheel diode (or synchronous MOSFET, in modern designs)
   L  = power inductor
   C  = output capacitor

The switch and diode together form a switching node — a single point that is either tied to V_in (switch on) or to ground (diode conducting). The inductor smooths current; the capacitor smooths voltage. That is the whole circuit.

The two phases of every switching cycle

Switch closed (on-time, fraction D of the period). The MOSFET pulls the switching node up to V_in. Voltage across the inductor is V_in − V_out (positive), so inductor current ramps linearly upward at dI/dt = (V_in − V_out) / L. Energy is flowing two places at once: into the load, and into the inductor's magnetic field (½ L I²).

Switch open (off-time, fraction 1 − D). The MOSFET turns off. But the inductor's current cannot change instantaneously — it would generate infinite voltage. So the current finds a new path: through the freewheeling diode, which forward-biases the instant the switch opens. Voltage across the inductor is now − V_out (negative), so the current ramps linearly back down at dI/dt = − V_out / L. The inductor is now delivering its stored energy to the load.

The load sees a current that ripples between I_max and I_min around the average I_load. The output capacitor swallows the ripple and presents a nearly DC voltage to the load. From the load's point of view it is connected to a near-perfect DC source; from the input's point of view, current is drawn only in bursts during the on-time. Both sides see clean DC, separated by the switching action of the LC filter.

The duty-cycle equation

In steady state, the average voltage across an inductor must be zero. (Otherwise its current would grow without bound — flux would integrate forever.) The switch node averages D × V_in. The inductor's other end is V_out. So:

V_inductor_avg = D · V_in − V_out = 0
                ⇒  V_out = D · V_in
                ⇒  D = V_out / V_in

This is the central equation of the buck converter, valid in continuous-conduction mode. A 50% duty cycle on 12 V gives 6 V. To regulate, the controller measures V_out, compares to a reference, and nudges D up or down. A typical voltage-mode controller is just a high-bandwidth feedback loop: error amplifier → compensator → PWM comparator → MOSFET driver.

CCM vs DCM

The V_out = D × V_in result assumes the inductor current never falls to zero — continuous-conduction mode. At light load, ripple amplitude doesn't shrink (it's set by V_in, V_out, L, f_sw) but the average drops, and eventually the trough of the ripple touches zero. From that load downward you're in discontinuous-conduction mode — the inductor fully demagnetises, sits idle for part of the period, and the transfer function becomes load-dependent.

Mode	Inductor I	Transfer function	Typical regime	Behaviour
CCM	Always > 0	V_out = D · V_in	Heavy load	Clean, predictable, stable feedback
DCM	Returns to 0 every cycle	Depends on L, f, load	Light load	Higher light-load efficiency, harder to compensate
Boundary (BCM)	Touches 0 at one instant	The CCM/DCM hinge	Critical load	Design point for some specialised topologies
Pulse-skipping (PFM)	Bursts, then idle	Skipped cycles regulate	Very light load	Maintains efficiency near no-load

Most converters are designed to sit in CCM at full load — typically with ripple ΔI_L = 20–40% of I_load_max — and slide gracefully into DCM or PFM at light load to keep efficiency from collapsing during sleep states.

Synchronous buck — kill the diode

The freewheel diode in the textbook topology has one job: conduct the inductor current during the off-time. A Schottky drops about 0.4 V. At 50 A that's 20 W of conduction loss during the off-time fraction — which, when V_out is small relative to V_in, dominates total loss.

Replace the diode with a second MOSFET, gated on during the off-time, and the voltage drop becomes I × R_DS(on). For a 2 mΩ low-side FET at 50 A: 50 × 50 × 0.002 = 5 W during the same off-fraction. 75% improvement, just by spending a few cents more on silicon and a gate-driver pin. Every modern point-of-load regulator is synchronous.

   V_in ──[HS FET]──┬──UUUU──┬── V_out
                    │         │
                    ├─[LS FET]┤  (replaces diode)
                    │         ═ C
                   GND       GND

   Gate drive: HS and LS alternate, with dead-time to avoid shoot-through.

The two switches must never conduct simultaneously — even nanoseconds of overlap shorts V_in directly to ground. The gate driver inserts dead-time, typically 20–80 ns, where both FETs are off and the inductor current freewheels briefly through the low-side FET's body diode. That body-diode conduction is its own minor loss, which is why high-efficiency designs use FETs with low Q_rr and tune dead-time aggressively.

Multiphase buck — the CPU VRM

A modern x86 CPU draws upwards of 200 A at about 1 V — over an order of magnitude more than a single buck stage can comfortably handle. The fix is to put N identical synchronous buck stages in parallel, each running 360°/N out of phase with its neighbours, and tie their outputs together.

This is the architecture of every CPU voltage regulator module (VRM) you'll see on a motherboard. An 8-phase VRM around an Intel CPU socket has eight power inductors arranged around the perimeter, each driven by its own MOSFET pair, all controlled by a single multi-phase PWM IC.

Property	Single-phase	N-phase interleaved
Current per inductor	I_load	I_load / N
Ripple frequency at output	f_sw	N · f_sw
Peak-to-peak output ripple	ΔI_L / (8 C f_sw)	≈ ΔI_L / (8 C N² f_sw)
Transient response	Single-stage bandwidth	Effectively N× faster
BOM	1 inductor, 2 FETs, 1 driver	N inductors, 2N FETs, N drivers + controller

The interleaving trick is what makes multiphase magic: when one phase is in its on-time, the others are off, so their currents partially cancel at the output node. Effective ripple frequency rises N times, peak-to-peak ripple drops roughly N², and you can use much smaller bulk capacitors. Servers run 16-phase and 32-phase VRMs at the same trick, just scaled up.

Worked example: a 12 V → 5 V, 3 A bench supply

Design a synchronous buck for a USB hub: V_in = 12 V (nominal), V_out = 5 V, I_load = 3 A max, f_sw = 500 kHz, ΔI_L = 30% of I_load.

Duty cycle. Ignoring drops, D ≈ V_out / V_in = 5 / 12 = 0.417, so the switch is on for about 41.7% of every period.

Period. T = 1 / f_sw = 2.0 µs. On-time t_on = D · T = 833 ns.

Inductor. ΔI_L target = 0.3 × 3 = 0.9 A. From dI/dt = (V_in − V_out) / L during on-time:

L = (V_in − V_out) · t_on / ΔI_L
  = 7 V · 833 ns / 0.9 A
  = 6.5 µH

Round up to a standard 6.8 µH shielded power inductor rated for at least 3 + 0.45 = 3.5 A peak (or, more conservatively, the I_sat rating sits above peak by 30%+).

Output capacitor. Choose 2% peak-to-peak ripple voltage, so ΔV_out_target = 100 mV. ESR dominates at moderate ripple:

ΔV_out ≈ ΔI_L · ESR + ΔI_L / (8 · C · f_sw)
        100 mV = 0.9 · ESR + small capacitive term
        ⇒ ESR < 50 mΩ, C ≥ 22 µF for transient margin

Two parallel 22 µF X7R MLCCs (ESR a few mΩ each) easily clear the spec.

Switching loss. Each MOSFET transition dissipates roughly ½ V_in · I_load · t_trans · f_sw. For a 30 ns transition: 0.5 · 12 · 3 · 30 × 10⁻⁹ · 500 × 10³ = 0.27 W per FET. Combined with conduction loss in both FETs (about 0.15 W) and inductor DCR loss (50 mΩ × 3² ≈ 0.45 W), total loss is around 1.1 W. Output power is 5 × 3 = 15 W; efficiency ≈ 15 / (15 + 1.1) ≈ 93%.

Where the missing 5% goes

The 5–10% of power a real buck doesn't deliver to the load shows up as heat in five places:

• MOSFET conduction loss. I² · R_DS(on) during the on-time. Falls with better silicon (GaN beats Si beats older Si) and parallel devices.
• MOSFET switching loss. Energy dumped each time V_DS swings across the channel while I_D is non-zero. Scales linearly with f_sw and roughly with V_in². Mitigated by ZVS (zero-voltage switching) and quasi-resonant topologies.
• Inductor DCR. Wire resistance × I². Bigger copper, lower DCR. Easy to fix at low frequency, harder at high frequency where skin effect bites.
• Inductor core loss. Hysteresis and eddy currents in the magnetic core. Climbs with frequency and ripple. Ferrite for high-f, powder iron for high-DC-bias.
• Output capacitor ESR. ΔI_L² · ESR. Modern MLCCs essentially eliminate this; older electrolytics dominated it.

The optimisation knobs — frequency, inductor value, FET selection, layout parasitics — all trade these losses against each other. Higher frequency shrinks magnetics but raises switching loss. Lower R_DS(on) lowers conduction loss but raises gate charge and switching loss. The art of buck design is finding the local minimum for your particular V_in, V_out, I_load, and cost budget.

Variants and cousins

• Asynchronous (diode) buck. The textbook version with a freewheeling diode. Still common at low load currents where the diode loss is tolerable and you want to save the gate-driver pin.
• Synchronous buck. Diode replaced by a low-side MOSFET. The default for any modern point-of-load.
• Multiphase synchronous buck. N interleaved synchronous bucks for very high current. CPU and GPU VRMs.
• Coupled-inductor buck. The N inductors of a multiphase share a common core. Lower ripple, smaller total inductance, but locked phase relationships. Used in space-constrained server VRMs.
• Trans-inductor voltage regulator (TLVR). Recent Intel- and AMD-driven topology that couples every inductor through a tiny secondary winding to a single "compensator" inductor. Even faster transient response than coupled-inductor; mandatory at 1 kA core currents.
• Two-stage cascaded buck. A first stage 48 V → 12 V intermediate bus, then a second stage 12 V → 1 V at the load. Standard in modern hyperscale datacentres because copper bus losses scale as 1/V² and 48 V cuts I²R losses 16× versus 12 V distribution.
• Bidirectional buck/boost. The same hardware run as a buck one way, boost the other. Used in EV traction inverters for regenerative braking, and in battery-charger second-stage power management.
• Hysteretic / constant-on-time buck. Skip the PWM ramp and turn the switch on each time output dips below a threshold. Excellent transient response, harder EMI, used in CPU VRMs and laptop charger ICs.

Where buck converters show up

• Every laptop charger. The 65 W USB-C brick steps mains → 20 V via an AC-DC stage, then the laptop steps 20 V → multiple internal rails (12, 5, 3.3, 1.8, 1.2, 1.0 V) through a stack of bucks on the motherboard. There are typically 8–15 separate buck converters inside a single laptop.
• CPU and GPU VRMs. Multi-phase synchronous buck arrays of 4 to 32 phases delivering 1 V at 100–600 A. The single biggest source of power-delivery innovation in consumer electronics.
• Smartphone PMICs. A single power-management IC integrates 10–20 buck converters into a chip the size of a Tic-Tac, generating every rail the SoC, modem, RF front-end, camera, and display need. Switching frequencies often above 3 MHz to keep the inductors small enough for phone PCB area.
• EV traction inverters and DC-DC. The 12 V auxiliary bus of an EV is generated from the 400 V (or 800 V) traction battery by a large bidirectional buck — often 1–3 kW continuous. Tesla, Lucid, Rivian, every major EV.
• Data-centre 48 V bus. Google's Open Compute Platform and AMD's SP3 server motherboards run a 48 V intermediate bus that's bucked down to processor voltages at each socket. The 48 V choice came from Google's recognition that 12 V bus losses dominated rack-level power waste.
• LED drivers. Constant-current buck driving a string of LEDs. The MR16-style retrofit bulbs you screw into a 12 V halogen socket are mostly a buck converter and an LED chain.
• Battery-powered everything. Wearables, sensors, IoT, drones. The output of any LiPo cell (3.7 V nominal) is bucked down to 1.8 V or 3.3 V for the microcontroller; the input to any USB charger is bucked from 5 V (or 20 V Power Delivery) to the cell's charge voltage.

Common pitfalls in buck design

• Inductor saturation under transient load. Picking L based on I_load_avg without checking I_peak under a worst-case transient. When the inductor saturates, dI/dt explodes, and the high-side FET sees enormous current spikes that blow it in microseconds.
• Layout-induced ringing. Stray inductance in the high-side gate loop or the V_in → HS FET → LS FET → GND switching loop causes V_DS ringing of 1.5–2× V_in. If V_in is 30 V and your FET is rated 40 V, the ringing pops it. Tight switching-node layout with ground-return planes is mandatory.
• Shoot-through during deadtime tuning. Too little dead-time and HS/LS conduct simultaneously — shorting V_in to ground for a few ns per cycle. The current spike kills efficiency and eventually melts something. Too much dead-time and body-diode loss climbs. Modern controllers auto-tune.
• Loop instability after MLCC voltage de-rating. Ceramic capacitors lose 50–80% of capacitance at rated DC bias. A 22 µF MLCC at 5 V might actually be 8 µF in circuit. Compensator gain-phase margins computed against the nameplate value can become unstable; measure actual capacitance at operating bias.
• EMI from the switching node. Every nanosecond of MOSFET switching radiates harmonics up to GHz. Without an input filter, a buck converter at 500 kHz looks like a radio jammer. FCC Part 15 / CISPR 22 conducted-emission compliance is a real design constraint, not an afterthought.
• Wrong-direction conduction at light load in synchronous mode. A pure synchronous buck will source current and sink it — meaning at very light load the LS FET pulls inductor current negative, pumping energy back from V_out to V_in and trashing efficiency. Solution: detect zero-crossing and turn LS off (a.k.a. "diode emulation mode" or DEM).

Historical context

The basic chopper-and-filter topology dates to early 20th-century mercury-arc traction converters, but the modern buck-converter recipe — high-frequency PWM, MOSFET switch, fast diode, small LC filter — emerged in the late 1960s with the first practical power transistors and switching-mode aerospace supplies. Robert Boschert's seminal paper "Design and Application of a Practical Switching Power Supply" (1979) and the founding of Linear Technology, Maxim, and Power Integrations in the late 1980s commoditised the silicon. By the 1990s a buck converter IC cost a dollar; by the 2010s a six-phase digital buck controller cost a few dollars.

The 2020s pushed the same fundamentals to extremes that the 1980s would have called impossible: GaN switches at 5 MHz, 16-phase VRMs delivering 1 kA, 99% efficient point-of-load modules. The textbook circuit at the top of this page hasn't changed in fifty years — the silicon under each component has.