Current Mirror

How a current mirror works

A current mirror exploits one fact about transistors: a MOSFET's drain current is a steep, repeatable function of its gate-source voltage V_GS, and a BJT's collector current is an equally repeatable function of its base-emitter voltage V_BE. If you can fix that control voltage precisely, you fix the current. A current mirror does exactly that by letting a known reference current generate the control voltage, then handing that voltage to a second, identical transistor.

The input transistor is wired diode-connected — its gate (or base) is tied to its own drain (or collector). Forcing a reference current I_REF through it pushes its V_GS to whatever value sustains exactly that current. Because the second transistor shares the same gate node and the same source rail, it sees the same V_GS, and if it is built identically it conducts the same current. The reference branch acts as a measuring stick; the output branch reads off that stick.

MOSFET mirror (saturation, square-law):

  I_D = ½ · µ·Cox · (W/L) · (V_GS − V_th)²

Both transistors share V_GS and V_th, so:

  I_OUT     (W/L)_2
  ───── =  ─────────
  I_REF     (W/L)_1

A 1:1 mirror copies the current; a 1:N mirror scales it.

The same idea works with bipolar transistors, where the controlling relationship is exponential rather than square-law:

BJT mirror (forward active):

  I_C = I_S · exp(V_BE / V_T)        V_T ≈ 25.9 mV at 300 K

Shared V_BE and matched I_S give:

  I_OUT     A_E2
  ───── ≈  ──────   (ratio of emitter areas)
  I_REF     A_E1

…minus a base-current error of 2/β for the simple two-transistor form.

Where the reference current comes from

A mirror only copies a current; something else must create the reference. The crude approach is a single resistor from the supply to the diode-connected transistor: I_REF ≈ (V_DD − V_GS) / R. With V_DD = 3.3 V, V_GS = 0.7 V and R = 26 kΩ this gives 100 µA — but it tracks supply voltage directly, so a 10% rail change moves the bias 10%. Real designs derive I_REF from a supply-independent source: a bandgap-referenced V_BE/R cell, a constant-g_m bias loop, or a precision external resistor. The mirror then fans that one good current out to a dozen bias points across the chip, each scaled to what its block needs.

What spoils the copy: matching, Early effect, and headroom

An ideal mirror would copy the reference exactly and hold it flat over any output voltage. Three real effects break that ideal:

• Mismatch. The two transistors must be identical. A threshold-voltage offset ΔV_th of even 5 mV against a (V_GS−V_th) overdrive of 200 mV produces roughly a 5% current error, since the error scales as 2·ΔV_th/(V_GS−V_th). On-chip layout fights this with common-centroid placement, identical orientation, dummy devices at the array edges, and large enough gate areas that random doping fluctuation averages out (Pelgrom's law: matching improves with √(W·L)).
• Channel-length modulation (Early effect). The output transistor's drain voltage is usually not equal to the input transistor's, and a higher drain voltage slightly widens the channel and lifts the current. This is the finite output resistance r_o = V_A/I. With an Early voltage V_A = 10 V at I = 50 µA, r_o = 200 kΩ, so a 1 V swing at the output changes the current by 5 µA — a 10% error in a simple mirror.
• Headroom. The output transistor must stay in saturation to act as a current source. A simple mirror needs only one V_DS,sat (≈ 0.2 V) of output headroom, which is its main virtue; a cascode mirror doubles that to ≈ 0.4 V in exchange for far higher output resistance.

Mirror topologies compared

	Simple (2T)	Cascode	Wide-swing cascode	Wilson (3T)	Beta-helper
Transistor count	2	4	4 (+bias)	3	3
Output resistance	ro	≈ gmro²	≈ gmro²	≈ βro/2 (BJT)	ro
Output headroom	~0.2 V	~0.4 V (2·VDS,sat)	~0.2 V	~0.3 V	~0.2 V
Input headroom	1 VGS	2 VGS	2 VGS	2 VBE	2 VBE
BJT base-current error	≈ 2/β	≈ 2/β	≈ 2/β	≈ 1/β²	≈ 1/β²
Best for	Compact biasing	High-gain stages	Low-voltage, high rout	Precision BJT mirror	Reducing BJT error

Worked example: a 1:4 MOSFET mirror

A bias cell delivers I_REF = 10 µA into a diode-connected NMOS M1 with W/L = 2/1. You need 40 µA to bias an output stage. Make the output transistor M2 four unit-devices in parallel, so (W/L)₂ = 8/1.

I_OUT = I_REF · (W/L)_2 / (W/L)_1
      = 10 µA · (8/1) / (2/1)
      = 40 µA

Now estimate the output-resistance error. Take V_A = 8 V:

  r_o2 = V_A / I_OUT = 8 V / 40 µA = 200 kΩ

If the output node swings 1 V away from the input node's V_DS:

  ΔI = 1 V / 200 kΩ = 5 µA   →  a 12.5% error.

Stacking a cascode (g_m·r_o ≈ 20) raises r_o to ~4 MΩ:

  ΔI = 1 V / 4 MΩ = 0.25 µA  →  a 0.6% error.

The lesson: the ratio is set by geometry and is very accurate, but holding the copied current flat across the output voltage is what separates a textbook mirror from a usable bias source — and that is the cascode's whole job.

Worked example: BJT base-current error

A simple npn mirror copies a 100 µA reference with transistors of β = 100. Both bases pull current from the reference node, so the reference must feed two collectors plus two bases:

I_REF = I_C + 2·I_B = I_C·(1 + 2/β)

  I_OUT = I_C = I_REF / (1 + 2/β)
        = 100 µA / (1 + 2/100)
        = 100 / 1.02
        = 98.04 µA       →  a 2.0% shortfall.

A beta-helper transistor supplies the base currents instead,
cutting the error to ≈ 2/β² = 2/10,000 = 0.02%:

  I_OUT ≈ 99.98 µA.

This base-current error is why precision BJT bias networks almost always use a beta-helper or Wilson mirror, and why MOSFET mirrors — whose gates draw no DC current — are inherently free of it.

Where current mirrors show up

• Op-amp tail and load. The active load of a differential pair is a current mirror that converts the pair's differential output into a single-ended signal while presenting high impedance. The tail current source is itself a mirror.
• Bandgap references. Mirrors force equal or ratioed currents through two branches whose V_BE difference generates the proportional-to-absolute-temperature term.
• Bias distribution. One master reference current is mirrored, scaled and routed to every analog block, so all blocks track together over temperature and process.
• Class-AB output stages. Mirrors set the quiescent current that keeps both output devices slightly on to avoid crossover distortion.
• DACs and translinear circuits. Binary- or thermometer-weighted mirror arrays produce precisely ratioed currents that sum into an analog output.

Failure modes and trade-offs

• Layout mismatch. Devices placed far apart, in different orientations, or near a heat source diverge in V_th and copy the current poorly. Fix with common-centroid layout, dummy fingers, and adequate gate area.
• Output transistor leaving saturation. If the output node droops below V_DS,sat, the mirror transistor enters the triode region and the current collapses far below the reference. Budget headroom for the worst-case output swing.
• Channel-length modulation drift. A simple mirror's current changes with output voltage; if a downstream stage needs a stable bias, the few-percent variation may dominate the error budget. Use a cascode.
• Thermal gradient. Self-heating in a nearby power device skews the matching; the two transistors must sit on the same isotherm.
• Startup lock-up. Self-biased mirror loops have a stable zero-current state. A startup circuit is needed to kick the loop into its intended operating point.
• Headroom vs. accuracy trade. Every accuracy improvement (cascoding, beta-helpers) costs supply voltage; in a 1.2 V process a stacked cascode may simply not fit, forcing a wide-swing variant.