Electrical
Flip-Flop
Bistable digital memory element — D, JK, SR, T variants
A flip-flop is a bistable digital circuit storing one bit of state. Two stable outputs (Q and not-Q) hold their values until clocked. Variants include SR (set-reset, basic latch), D (data, transparent on edge), JK (toggle when both inputs high), and T (toggle on every clock). Edge-triggered behavior distinguishes flip-flops from level-sensitive latches. Building block of registers, counters, state machines, and processor pipelines.
- OutputQ and complement Q-bar
- BistableTwo stable states — holds 1 bit
- TypesSR, D, JK, T
- TriggeringEdge-triggered (rising or falling clock)
- Built fromCross-coupled NAND or NOR gates
- ApplicationsRegisters, counters, state machines
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Why flip-flops matter
- Memory. Single-bit storage element of digital systems.
- Registers. Parallel groups hold multi-bit values.
- Synchronization. Edge-triggering aligns logic to a clock.
- State machines. Encode current state for sequential logic.
- Counters. Frequency division and event counting.
- Pipelines. Pipeline registers separate processor stages.
- Universal. Inside every CPU, FPGA, microcontroller.
Common misconceptions
- Latch equals flip-flop. Latches are level-sensitive, flip-flops edge-triggered.
- Setup/hold optional. Violations cause metastability and silent corruption.
- Outputs settle instantly. Clock-to-Q delay limits clock frequency.
- SR forbidden state harmless. Outputs race when inputs go inactive together.
- Asynchronous clear is free. Causes glitches if released near clock edge.
- Power-up state defined. Must explicitly reset; initial state is random.
Frequently asked questions
What's a flip-flop?
A bistable digital storage element holding one bit. Two stable output states, Q low or Q high, that persist until the clock triggers a change. Built from cross-coupled gates with feedback. Distinguishes from latches by edge-triggering. Foundation of registers, memory, and synchronous digital logic.
How does an SR latch work?
Two cross-coupled NOR or NAND gates. S (set) drives Q high. R (reset) drives Q low. Both low: holds previous state (memory). Both high simultaneously: forbidden state, outputs become indeterminate when inputs return. The basic building block. Adding clock gating yields a clocked SR latch.
What is a D flip-flop?
Data flip-flop. One data input D, one clock. On the active clock edge, Q takes the value of D and holds it until the next edge. Eliminates the SR forbidden state. Most common variant. Used in registers, shift registers, and pipeline stages. Setup and hold times specify when D must be stable around the clock edge.
How does a JK flip-flop differ?
Generalizes SR. J acts like set, K acts like reset. The forbidden combination (J=K=1) becomes useful: the output toggles on each clock edge. J=K=0 holds. J=1, K=0 sets. J=0, K=1 resets. Convenient for counters and toggle circuits. Slightly more complex internal logic than D.
What is a T flip-flop?
Toggle flip-flop. Single T input. T=1: output toggles on every clock edge. T=0: holds. Easily made from a JK by tying J and K together, or from a D with feedback through an XOR. Used in frequency dividers and counter stages.
What are setup and hold times?
Timing constraints. Setup time: data must be stable before the clock edge. Hold time: data must remain stable after the clock edge. Violating either causes metastability where Q oscillates or settles unpredictably. Synchronizers and double-flip-flop chains mitigate metastability when crossing clock domains.
How are flip-flops used in counters?
Chain of T flip-flops. Each clocked by the previous output gives a ripple counter. Each stage divides the frequency by two. N stages count to 2^N. Synchronous counters clock all stages from the master clock and use combinational logic to gate toggling, eliminating ripple delay. Foundation of timers and frequency dividers.