555 Timer

What the 555 timer actually is

Strip away the package and the 555 is a deceptively simple analog state machine. Three identical 5 kΩ resistors in series across the supply form a divider that taps off two reference voltages: 2/3 Vcc and 1/3 Vcc. (That ladder of three resistors is the origin of the "555" name.) Two comparators continuously compare an external capacitor's voltage against those two references. Their outputs drive a set-reset (SR) latch, whose state appears at the output pin through a push-pull stage and simultaneously controls a discharge transistor connected to pin 7.

Everything the 555 does follows from one loop: the external capacitor charges through a resistor toward Vcc, the upper comparator trips at 2/3 Vcc and resets the latch, the discharge transistor turns on and pulls the capacitor down, the lower comparator trips at 1/3 Vcc and sets the latch again. Because the comparator thresholds are fractions of the supply, the timing depends only on the external R and C and not on the supply voltage itself — the single most important property of the chip.

The eight pins

Pin	Name	Function
1	GND	Ground reference (0 V)
2	Trigger	Active-low input to the lower comparator; a level below 1/3 Vcc sets the latch and drives the output high
3	Output	Push-pull output, swings near 0 V to near Vcc, sinks/sources up to 200 mA
4	Reset	Active-low master reset; pull below ~0.7 V to force output low; tie to Vcc when unused
5	Control Voltage	Direct access to the 2/3 Vcc node; bypass with 10 nF or drive externally to modulate thresholds (PWM)
6	Threshold	Input to the upper comparator; when it exceeds 2/3 Vcc the latch resets and the output goes low
7	Discharge	Open collector of the internal discharge transistor; sinks the timing capacitor to ground when output is low
8	Vcc	Positive supply, 4.5–16 V for the bipolar NE555

Astable mode: the free-running oscillator

Connect Threshold (pin 6) and Trigger (pin 2) together to the capacitor, route the charging current through R1 then R2, and tap Discharge (pin 7) between R1 and R2. The capacitor now charges through R1 + R2 and discharges through R2 alone. There is no stable state — the output oscillates indefinitely.

Charge phase  (output HIGH): C charges 1/3 Vcc → 2/3 Vcc through (R1 + R2)
Discharge phase (output LOW): C discharges 2/3 Vcc → 1/3 Vcc through R2

t_high = ln(2) · (R1 + R2) · C  = 0.693 (R1 + R2) C
t_low  = ln(2) · R2 · C         = 0.693 · R2 · C

Period   T = t_high + t_low = 0.693 (R1 + 2R2) C
Frequency f = 1 / T = 1.44 / ((R1 + 2R2) C)
Duty cycle D = (R1 + R2) / (R1 + 2R2)

The 0.693 factor is just ln(2): charging an RC network from 1/3 to 2/3 Vcc always covers the same fraction of the exponential, regardless of supply. Because both R1 and R2 are in the charge path but only R2 is in the discharge path, the classic two-resistor astable can never reach exactly 50% duty — the high time always exceeds the low time. Adding a diode across R2 (so charging bypasses R2) decouples the two times and lets duty drop to or below 50%.

Worked example: a 1 kHz, ~50% blinker

Suppose you want a roughly 1 kHz square wave. Pick C = 100 nF and aim for R1 ≪ R2 so duty approaches 50%:

Choose C  = 100 nF   = 1 × 10⁻⁷ F
Choose R1 = 1 kΩ      (small, to push duty toward 50%)
Solve for R2 from f = 1.44 / ((R1 + 2R2) C):

  R1 + 2R2 = 1.44 / (f · C)
           = 1.44 / (1000 × 1 × 10⁻⁷)
           = 14,400 Ω
  2R2 = 14,400 − 1,000 = 13,400 Ω
  R2  = 6.7 kΩ  (use 6.8 kΩ standard value)

Recheck with R2 = 6.8 kΩ:
  T = 0.693 (R1 + 2R2) C
    = 0.693 (1,000 + 13,600) × 1 × 10⁻⁷
    = 0.693 × 14,600 × 1 × 10⁻⁷
    = 1.012 × 10⁻³ s
  f ≈ 988 Hz
  D = (1,000 + 6,800) / (1,000 + 13,600) = 53.4 %

Standard resistor values land within about 1% of the target frequency. The duty cycle sits at 53% — to bring it to 50% you would add the diode-across-R2 trick or move to a CMOS 555 with a separate charge/discharge topology.

Monostable mode: the one-shot

Tie Discharge (pin 7) and Threshold (pin 6) to the top of the timing capacitor, charge the capacitor through a single resistor R from Vcc, and feed a trigger to pin 2. At rest the discharge transistor clamps the capacitor at 0 V and the output sits low — the one stable state. A falling edge below 1/3 Vcc on pin 2 sets the latch: the output snaps high and the discharge transistor releases, so the capacitor begins to charge through R.

Capacitor charges from 0 toward Vcc through R.
Output stays HIGH until V_C reaches the 2/3 Vcc threshold:

  V_C(t) = Vcc (1 − e^(−t / RC))
  Set V_C = (2/3) Vcc:
    2/3 = 1 − e^(−t/RC)
    e^(−t/RC) = 1/3
    t = RC · ln(3) = 1.0986 · R · C  ≈  1.1 · R · C

Example: R = 100 kΩ, C = 10 µF
  t = 1.1 × 100,000 × 10 × 10⁻⁶
    = 1.1 s

The pulse width is set by R and C only; once the threshold is reached the latch resets, the output returns low, and the discharge transistor dumps the capacitor, ready for the next trigger. The trigger pulse must be shorter than the output pulse and must return above 1/3 Vcc, or the chip re-triggers and the output stays high (a common beginner failure).

Astable vs monostable vs bistable

	Astable	Monostable	Bistable (Schmitt)
Stable states	None — free-runs	One (output low)	Two (set / reset)
Output	Continuous square wave	One pulse per trigger	Latched level
Timing element	R1, R2, C	R, C	None — no capacitor
Key equation	f = 1.44/((R1+2R2)C)	t = 1.1·R·C	Toggles on trigger/reset
Charge path	R1 + R2	R	—
Discharge path	R2	internal (dump)	—
Typical use	Clocks, tone gen, LED flashers, PWM	Debounce, delay, pulse stretch	Latching switch, set-reset memory

Bipolar NE555 vs CMOS variants

Parameter	NE555 (bipolar)	TLC555 / LMC555 (CMOS)
Supply voltage	4.5–16 V	2–15 V (TLC555 down to 2 V)
Supply current (quiescent)	~3–10 mA	~170 µA (TLC555)
Max frequency	~500 kHz	~1.5–3 MHz
Output current	±200 mA	±100 mA source, less sink
Discharge current spike	Large (Vcc droop)	Small
Trigger / threshold input current	~0.5 µA (bias)	~pA (very high impedance)
Best for	Driving relays, LEDs, motors directly	Battery, high-frequency, long RC with small C

The bipolar 555 draws a current spike each time the discharge transistor fires, which can drag the supply rail down and inject noise — always decouple Vcc with at least 100 nF close to pin 8. The CMOS versions almost eliminate that spike and tolerate the megaohm timing resistors needed for very long delays, because their threshold/trigger inputs draw essentially no bias current. The trade-off is reduced output drive: a CMOS 555 will not switch a relay coil directly the way an NE555 can.

Pin 5 and pulse-width modulation

Pin 5 exposes the 2/3 Vcc node of the divider. Drive it with an external voltage and you move the upper comparator threshold up or down, which changes how long the capacitor must charge before the output flips. Feed an audio or control signal into pin 5 of an astable 555 and the duty cycle — and pulse width — follows that signal: you have built a PWM modulator from one chip. When you are not using pin 5, leave a 10 nF bypass capacitor on it to ground; otherwise supply noise on that node directly jitters the output period.

Failure modes and design traps

• Floating Reset pin. Pin 4 is active-low and high-impedance. Left floating it picks up noise and randomly chops the output low. Always tie it to Vcc (or a deliberate reset signal) through a pull-up.
• Supply droop on discharge. The bipolar discharge transistor sinks a large transient current each cycle; without a Vcc decoupling capacitor the supply dips and the comparator references move, causing period jitter and even double-triggering. A 100 nF (plus bulk electrolytic) across pins 8 and 1 fixes it.
• Electrolytic capacitor leakage. Long timing periods need large C, usually electrolytic. Their leakage current and ±20% tolerance make long delays imprecise — a "1 minute" timer can drift tens of seconds. Use film capacitors and large R, or a CMOS 555 that tolerates megaohm resistors with small film caps.
• Re-triggering in monostable mode. If the trigger pulse on pin 2 stays below 1/3 Vcc longer than the intended output pulse, the output is held high and never times out. Differentiate the trigger with an RC edge-detector so only the falling edge reaches pin 2.
• Duty cycle stuck above 50%. The classic two-resistor astable always has the charge path longer than the discharge path. To get ≤50% duty, add a diode across R2 so charge and discharge use independent resistances, or use a separate-path CMOS topology.
• Threshold and trigger fighting at high frequency. Above a few hundred kHz the ~100 ns internal propagation delay becomes a meaningful fraction of the period, distorting the waveform and shifting frequency. Move to a CMOS 555 or a dedicated oscillator IC.

Why the 555 still ships in billions

The 555 survives because its timing depends only on external R and C and ratios of internal resistors, never on absolute device parameters or supply voltage. That makes it astonishingly tolerant of process variation, temperature, and rail noise — temperature drift is around 50 ppm/°C, and the period barely changes from 5 V to 15 V. For a one-shot delay, a slow clock, a tone, a flasher, a PWM dimmer, or a debounce, it is faster to design, cheaper, and more robust than a microcontroller — which is why a chip from 1972 is still in active production today.