LDO Voltage Regulator

How an LDO regulates

Every LDO is a feedback loop wrapped around one current-controlling element. Four pieces do the work: a pass transistor in series between input and output, a precision voltage reference, an error amplifier, and a feedback divider that samples the output. The loop has exactly one job — keep the sampled output equal to the reference — and it does that by continuously adjusting how hard the pass transistor conducts.

The reference (almost always a bandgap, around 1.2 V, chosen because it is nearly independent of temperature) sets the target. The divider scales the output down to that same level. The error amplifier subtracts the two and drives the pass transistor's gate so that any difference shrinks toward zero. If the output sags under a heavier load, the divided sample drops below the reference, the amplifier turns the pass transistor on harder, and the output recovers. The whole correction happens in microseconds.

With high loop gain, the steady-state result is simple:

At balance the divided output equals the reference:

  V_OUT · R2/(R1 + R2) = V_REF

Solving for the output:

  V_OUT = V_REF · (1 + R1/R2)

Example: V_REF = 1.2 V, R1 = 175 kΩ, R2 = 100 kΩ
  V_OUT = 1.2 · (1 + 1.75) = 1.2 · 2.75 = 3.3 V

A fixed-output LDO simply integrates R1 and R2 on-chip; an adjustable LDO brings the feedback node out to a pin so you pick R1/R2 yourself. (Some adjustable parts instead sense across a low-side resistor and target a fixed reference voltage at the ADJ pin — the algebra is the same.)

Dropout voltage and the pass transistor

The headline spec is in the name. Dropout voltage is the smallest input-to-output difference at which the loop can still regulate. As V_IN falls toward V_OUT, the error amplifier drives the pass transistor harder and harder until it is fully on — at that point the transistor is just a small resistance, R_DS(on) for a MOSFET, and the output becomes:

In dropout, the pass device is fully on:

  V_OUT = V_IN − I_LOAD · R_DS(on)

So the dropout voltage scales with load current:

  V_DROPOUT = I_LOAD · R_DS(on)

Example: R_DS(on) = 0.5 Ω, I_LOAD = 300 mA
  V_DROPOUT = 0.3 A · 0.5 Ω = 0.15 V = 150 mV

The choice of pass transistor is the single biggest design decision and explains why "low dropout" is even possible. A classic 7805-style regulator uses an NPN Darlington pass stage referenced to the output; its dropout is two base-emitter drops plus a saturation voltage — around 2 V — which is terrible. Replace it with a single PMOS pass transistor and the dropout collapses to I_LOAD × R_DS(on), often well under 200 mV. That swap is the entire reason the LDO category exists.

Pass element	Dropout	Drive requirement	Stability vs. C_OUT ESR	Quiescent current
NPN Darlington (old 7805)	~2 V (high)	Base current from output	Tolerant	Moderate
Single NPN	~1 V	Base current (steals from load)	Tolerant	Moderate
PMOS	I·R_DS(on), <200 mV	Voltage-driven gate (no DC current)	Often needs ESR zero or internal comp.	Low (µA possible)
NMOS (needs charge pump)	Very low, <100 mV	Gate above V_IN → charge pump	Easier (low output impedance)	Higher (pump runs)

The PMOS pass transistor is the workhorse of modern LDOs. It needs no DC gate current, so quiescent current can drop to microamps, but its high output impedance puts a pole near the output that complicates loop stability — the reason output-capacitor specs are so strict (see below). NMOS-pass LDOs achieve the lowest dropout and easiest stability but need a charge pump to drive the gate above the input rail, raising quiescent current.

Efficiency: the price of being linear

An LDO does not store and switch energy; it simply absorbs the difference between input and output as heat. That makes its efficiency brutally easy to compute and impossible to escape:

Ignoring quiescent current (I_Q << I_LOAD):

  η = P_OUT / P_IN = (V_OUT · I_LOAD) / (V_IN · I_LOAD) = V_OUT / V_IN

Power burned in the regulator:

  P_DISS = (V_IN − V_OUT) · I_LOAD + V_IN · I_Q

Example A — good fit:  3.6 V → 3.3 V at 200 mA
  η = 3.3/3.6 = 92%
  P_DISS = 0.3 V · 0.2 A = 60 mW   (trivial)

Example B — bad fit:  12 V → 3.3 V at 200 mA
  η = 3.3/12 = 28%
  P_DISS = 8.7 V · 0.2 A = 1.74 W  (needs heatsinking!)

This is the heart of every LDO design trade-off. Use an LDO when V_IN is close to V_OUT, when the load is modest, or when noise matters more than efficiency. The 1.74 W in Example B would push a small SOT-23 package far past its thermal limit; that application wants a buck converter instead. The thermal check is unavoidable: P_DISS times the package thermal resistance θ_JA (often 50–250 °C/W for small SMD parts) must keep the junction below its rated maximum, typically 125 °C.

Regulation, PSRR and noise

Three specs describe how good the regulated voltage actually is:

• Line regulation — how much V_OUT moves when V_IN changes. A typical figure is a fraction of a percent, e.g. 0.05%/V. High DC loop gain makes this excellent.
• Load regulation — how much V_OUT moves from no-load to full-load. Often a few millivolts. It is the output set by the loop's finite gain and the pass transistor's transconductance.
• PSRR (power-supply rejection ratio) — how much input ripple is rejected at the output, in dB. A good LDO gives 60–80 dB at low frequency, so 100 mV of input ripple becomes 0.1–0.01 mV out. PSRR falls at high frequency because the feedback loop runs out of gain above its bandwidth (typically tens of kHz), so the output capacitor must take over the rejection there.

Output noise is separate from PSRR: it is the noise the LDO generates itself, dominated by the bandgap reference. Low-noise LDOs add an external "noise-reduction" or "bypass" capacitor on the reference to filter it, reaching figures like 4–20 µV_RMS over 10 Hz–100 kHz. This is why a clock oscillator, ADC reference, PLL or RF VCO is almost always powered through a dedicated low-noise LDO rather than straight off a switcher rail.

	LDO (linear)	Buck converter (switching)	Standard linear (7805-class)
Efficiency	V_OUT/V_IN (poor at big ratios)	85–95% across wide ratio	V_OUT/V_IN (poor; high dropout)
Min. headroom	0.1–0.3 V	n/a (can step up or down)	~2 V
Output noise	Very low (µV-class)	Switching ripple (mV)	Low
External parts	1–2 capacitors	Inductor + caps + switch	1–2 capacitors
EMI	Negligible	Radiated/conducted at f_SW	Negligible
Transient response	Fast (µs), tight	Limited by inductor + loop	Moderate
Best use	Clean rails near V_IN; post-switcher cleanup	Large step-downs, high current	Legacy, cheap, headroom available

Worked example: a 3.3 V analog rail

An RF receiver needs a clean 3.3 V at up to 150 mA from a 3.6 V Li-ion rail that already carries 80 mVpp of switching ripple from an upstream buck. Pick an LDO with 120 mV dropout at 150 mA, 70 dB PSRR at 1 kHz, and I_Q = 50 µA.

Headroom check:
  V_IN − V_OUT = 3.6 − 3.3 = 0.30 V  >  0.12 V dropout  ✓ regulates

Thermal check (worst case, full load):
  P_DISS = (3.6 − 3.3) · 0.15 + 3.6 · 50e-6
         = 0.045 W + 0.00018 W ≈ 45 mW
  With θ_JA = 200 °C/W:  ΔT = 0.045 · 200 = 9 °C rise  ✓

Ripple rejection:
  70 dB → ratio 10^(70/20) ≈ 3160×
  80 mVpp in → 80/3160 ≈ 25 µVpp out  ✓ quiet enough for RF

Efficiency:
  η ≈ 3.3/3.6 = 92%

The LDO is the right tool here: tiny headroom, modest current, and the load demands quiet. A buck converter would be more efficient but would inject its own ripple right where it hurts.

Failure modes and trade-offs

• Thermal shutdown / runaway. The most common real-world failure is overheating. At large V_IN − V_OUT and high current, P_DISS bakes the die; the part hits thermal shutdown (usually ~150–165 °C) and the output collapses, recovering only after it cools — a stuttering rail. Always run the θ_JA math, not just the electrical math.
• Output-capacitor instability. An LDO is a control loop. PMOS-pass parts with an ESR-dependent stabilizing zero can oscillate if you fit a too-low-ESR ceramic cap, or a too-large/too-small value. Always honor the datasheet's C_OUT value and ESR window; internally-compensated modern LDOs relax this but still specify a minimum capacitance.
• Insufficient headroom (dropout). If V_IN dips below V_OUT + V_DROPOUT — say a battery sagging under a GSM transmit burst — regulation is lost and the output droops with the input. Size the input rail for worst-case dips, not nominal.
• PSRR collapse at high frequency. An LDO cannot reject ripple above its loop bandwidth. If you place it after a 2 MHz switcher expecting it to scrub the fundamental, it won't — the output capacitor must handle that band. Choose an LDO with PSRR specified at your switcher's frequency.
• Reverse current and input dips. If V_OUT exceeds V_IN (input shorts to ground, or a held-up output cap), the body diode of a PMOS pass transistor can conduct backward and damage the part unless reverse-current protection is present.
• Quiescent-current drain. A few-mA I_Q is invisible at 150 mA load but dominates a microamp standby budget. For always-on/IoT, a high-I_Q LDO can flatten a coin cell in weeks; pick a micropower part (I_Q of 1–25 µA) and accept its slower transient response.