Phase-Locked Loop

What a phase-locked loop actually does

Picture two signals: a clean reference — say a 10 MHz crystal oscillator — and a tunable oscillator whose frequency wanders with temperature, supply voltage, and age. You want the second oscillator to hold the first one's frequency with no drift, even though the second oscillator is sloppy on its own. The brute-force answer would be to build a perfect oscillator. The phase-locked loop answer is cheaper and far more powerful: wrap the sloppy oscillator in a feedback loop that continuously measures how far its phase has slipped from the reference and nudges it back.

A PLL is exactly that loop. It has three blocks in a ring. A phase detector compares the phase of the reference against the phase of the oscillator's output and emits an error signal proportional to the difference. A loop filter — a low-pass network — smooths that error into a slowly varying DC control voltage. That control voltage drives a voltage-controlled oscillator (the VCO), whose frequency rises and falls with the voltage. Negative feedback closes the loop: if the VCO runs fast, its phase races ahead, the phase detector reports a growing error, the control voltage drops, and the VCO slows down — and vice versa. The loop settles into a steady state where the phase error is constant, which can only happen when the two frequencies are exactly equal. That is frequency lock.

The deep idea is that phase and frequency are not independent. Frequency is the time derivative of phase, ω = dφ/dt. If the phase error between reference and VCO is holding constant, its derivative is zero, which means the two frequencies are identical to the last decimal place — not approximately, exactly. A control loop that merely held frequency would always have some residual error; a loop that holds phase drives the frequency error to zero as a mathematical consequence. That is why we lock phase, not frequency, and why the device is named for the phase.

The three blocks in detail

The phase detector. The simplest is an analog multiplier (a mixer): multiply two sinusoids of the same frequency and the output contains a DC term proportional to cos of the phase difference, plus a double-frequency term the loop filter throws away. An XOR gate does the same job for square waves. Modern synthesizers almost universally use a phase-frequency detector (PFD): a pair of edge-triggered flip-flops that produce separate UP and DOWN pulses telling the loop not just how far out of phase the signals are, but which one is leading. Because the PFD senses frequency as well as phase, it can pull the loop in from a cold start over the VCO's entire tuning range — it never gets confused by a beat note the way a multiplier does.

The loop filter. This is the brain of the loop. It integrates the phase-detector error into the VCO control voltage and sets the loop bandwidth, damping, and noise behavior. In a charge-pump PLL the PFD's UP/DOWN pulses switch a current source that dumps charge onto a capacitor; the resistor-capacitor network across that capacitor forms the loop filter. The filter's job is to pass the slow average of the error (which carries the real frequency information) while rejecting the fast reference-rate ripple (which would smear the output spectrum with spurs).

The VCO. The voltage-controlled oscillator turns control voltage into frequency with a gain called K_VCO, in radians per second per volt (or Hz/V). A typical integrated LC-VCO might tune from 2.2 to 2.6 GHz over a 0 to 1.2 V control range, giving K_VCO ≈ 330 MHz/V. The VCO is itself an integrator in the loop's control-theory sense, because it integrates frequency into phase. That built-in integration is why even the simplest PLL is a type-1 system and why the loop has the order and stability character it does.

The governing equations — with real numbers

Linearize the loop around lock, where phase errors are small. Each block becomes a gain or a transfer function in the phase domain. The phase detector has gain K_d (volts per radian), the loop filter has transfer function F(s), and the VCO converts control voltage to phase with transfer function K_VCO/s — the 1/s is the integration of frequency into phase. The open-loop gain around the ring is:

G(s) = K_d · F(s) · (K_VCO / s) / N      (N = feedback divide ratio)

For a passive lead-lag loop filter F(s) = (1 + sτ₂)/(sτ₁), the closed-loop response is the textbook second-order system:

H(s) = (2ζω_n s + ω_n²) / (s² + 2ζω_n s + ω_n²)

  natural frequency:   ω_n = sqrt( K_d · K_VCO / (N · τ₁) )
  damping factor:      ζ   = (τ₂ / 2) · ω_n

These two numbers — ω_n and ζ — decide everything. The standard maximally-flat choice is ζ = 0.707, which gives a fast lock with minimal overshoot. Let's size a real loop. Suppose a 2.4 GHz Wi-Fi local oscillator from a 10 MHz reference (N = 240), a charge-pump current of 1 mA, a VCO gain of 30 MHz/V, and we want a 100 kHz loop bandwidth:

Reference:        f_ref   = 10 MHz
Divide ratio:     N       = 240   →   f_VCO = 2.400 GHz
VCO gain:         K_VCO   = 30 MHz/V = 1.88e8 rad/s/V
Charge pump:      I_cp    = 1 mA
Phase-det gain:   K_d     = I_cp / (2π) = 159 µA/rad

Loop bandwidth:   ω_n     ≈ 2π · 100 kHz = 6.28e5 rad/s
Damping:          ζ       = 0.707  (Butterworth response)

Loop-filter cap:  C1      = K_d · K_VCO / (N · ω_n²)
                          = (1.59e-4 · 1.88e8) / (240 · (6.28e5)²)
                          ≈ 316 pF
Loop-filter R:    R       = 2ζ / (ω_n · C1) ≈ 7.1 kΩ

Reference rule:   ω_n must be ≲ f_ref / 10 = 1 MHz   ✓ (100 kHz, stable)
Lock time:        t_lock  ≈ 4 / (ζ · ω_n) ≈ 9 µs

That 9-microsecond lock time is why a phone can scan channels: each frequency hop reprograms N, and the loop re-locks in under ten microseconds. Push the loop bandwidth too close to the reference and the discrete sampling of the phase detector at 10 MHz adds delay, phase margin collapses, and the loop rings or breaks into oscillation — that is the entire reason for the ω_n ≲ f_ref/10 rule.

Frequency synthesis — multiplying a crystal to gigahertz

The single most common use of a PLL is as a frequency synthesizer. Drop a digital divide-by-N counter into the feedback path between the VCO and the phase detector. Now the phase detector compares f_ref against f_VCO/N, and lock forces:

f_VCO = N × f_ref

A 10 MHz crystal and N = 240 give 2.4 GHz. Change N to 241 and the output steps to 2.41 GHz. The output inherits the crystal's parts-per-million accuracy and long-term stability while landing on any channel a programmable integer allows. That is how a CPU turns a 100 MHz board clock into a 4.0 GHz core clock (N = 40), how a radio hops channels, and how an FPGA generates a dozen unrelated clock domains from one oscillator.

The catch is resolution: the channel spacing equals f_ref, so 25 kHz cellular channels would force a 25 kHz reference — and a 25 kHz reference forces a loop bandwidth under a few kilohertz, which locks slowly and lets VCO noise dominate. The fix is the fractional-N synthesizer: a delta-sigma modulator dithers N between, say, 240 and 241 so the time-averaged divide ratio is a fraction like 240.04. That gives sub-hertz frequency resolution while keeping the reference at a brisk 10 or 26 MHz and the loop bandwidth wide enough to lock fast. The price is fractional spurs, which the delta-sigma noise shaping pushes to high offset frequencies where the loop filter can attenuate them.

Lock range, capture range, and acquisition

Two ranges describe how a PLL grabs and holds a signal, and confusing them is a classic beginner error.

• Lock range (hold/tracking range). Once locked, the band of input frequencies the loop will follow as the input drifts. Limited only by the VCO tuning range in a type-2 loop. Wide.
• Capture range. Starting from unlocked, the band of input frequencies from which the loop can acquire lock. Always narrower than the lock range, and set by the loop filter bandwidth.

The asymmetry has a physical cause. When the loop is far off frequency, the phase-detector output is a fast beat note at the difference frequency. The loop filter heavily attenuates anything faster than its bandwidth, so only a small net DC component survives to pull the VCO toward the reference. Pulling into lock therefore only works over a narrow band where that residual pull is strong enough. Once locked, the loop only has to correct slow drift, so it tracks across the much wider lock range. A phase-frequency detector sidesteps the whole problem: because it senses which signal is faster, it produces a sustained DC push toward lock over the full VCO range, so a charge-pump PFD loop's capture range effectively equals its lock range.

Type and order — why type-2 dominates

The type of a PLL counts the integrators in the open-loop path. Every loop has at least one — the VCO. A type-1 loop has only that integrator plus a passive RC filter; it locks with a static phase error that grows with frequency offset, and it cannot track a steadily ramping frequency without an ever-growing error. A type-2 loop adds a second integrator (the charge pump dumping onto a capacitor, or an active op-amp integrator). The second integrator forces the steady-state phase error to zero for any fixed frequency and lets the loop follow a frequency ramp with constant error. Nearly every modern synthesizer is type-2 because zero static phase error means the output is exactly N × f_ref with no offset — but the second integrator adds 90° of phase lag, so the loop filter must contribute a zero (the series resistor) to claw back phase margin, or the loop goes unstable.

PLL vs the alternatives

A PLL is one of several ways to generate or recover a frequency. The comparison below shows where it wins and where a different architecture is the right call.

Property	Phase-locked loop (PLL)	Free-running crystal/LC oscillator	Direct digital synthesis (DDS)	Delay-locked loop (DLL)
Output frequency	N × reference, MHz–tens of GHz	Fixed, set by the crystal cut	Up to ~½ the DAC clock	Equals reference (phase-shifted)
Frequency agility	Reprogram N; locks in µs	None — one frequency only	Instant, sub-Hz steps	None — it shifts phase, not frequency
Phase noise near carrier	Tracks the clean reference	Excellent (crystal) / poor (LC)	DAC quantization + spurs	Very low — no VCO to integrate noise
Builds a frequency multiplier?	Yes — the standard way	No	No (synthesizes directly)	No (clock multiply via edge combining)
Stability risk	Yes — loop can ring/oscillate	None	None (open-loop)	Lower — first-order, unconditionally stable
Typical use	RF synthesizers, CPU clocks, CDR, FM demod	Reference clocks, simple timing	Signal generators, radar, AWGs	Clock de-skew, DDR memory phase alignment

The DDS comparison is the most instructive. A DDS computes a phase ramp digitally and feeds it to a DAC, giving instantaneous frequency changes and millihertz resolution — but it is limited to roughly half the DAC clock rate and carries quantization spurs. A PLL has no such frequency ceiling: its output is whatever the VCO can reach, into the tens of gigahertz, and its near-carrier phase noise is set by the clean reference rather than DAC bits. That is why a 28 GHz millimeter-wave 5G radio uses a PLL, not a DDS, for its local oscillator. A delay-locked loop, by contrast, is the right tool when you only need to phase-align an existing clock — DDR memory interfaces use DLLs to de-skew the data strobe — because a DLL has no VCO and so cannot accumulate phase noise or ring the way a PLL can.

Where phase-locked loops actually show up

• Radio and cellular synthesizers. The local oscillator that selects a channel in every Wi-Fi, Bluetooth, and 4G/5G transceiver is a fractional-N PLL. A handset retunes the LO in microseconds to hop channels, and the same chip might run several PLLs for receive, transmit, and clocking.
• CPU, GPU, and FPGA clock generation. A processor multiplies a 25 or 100 MHz board crystal up to multi-gigahertz core clocks through on-die PLLs, and uses additional PLLs (and DLLs) to skew-align clock domains so flip-flops across the die latch together.
• Clock-and-data recovery (CDR). High-speed serial links — USB, SATA, PCIe, and 100/400-gigabit Ethernet SerDes — carry no separate clock line. A CDR PLL extracts the bit clock directly from the data transitions, locking to the embedded timing so the receiver can sample each bit at its center.
• FM and FSK demodulation. Lock a PLL to an FM carrier and the VCO control voltage is the demodulated audio — because the loop must vary its control voltage exactly to follow the carrier's frequency deviation. The classic 565 PLL chip was used this way for decades.
• Grid-tie inverters and motor drives. Solar and wind inverters use a PLL to lock onto the 50/60 Hz mains phase so they inject current synchronously with the grid voltage; field-oriented motor control uses a PLL to track rotor angle.
• Instrumentation and timing. Lock-in amplifiers, atomic-clock disciplining, and GPS-disciplined oscillators all use PLLs to transfer the stability of one reference onto another oscillator.

Failure modes and trade-offs

• Loop instability. A type-2 loop with too little phase margin rings on every frequency hop or, worse, breaks into sustained oscillation. The fix is a loop-filter zero (series R) placed below the loop bandwidth and a damping factor near 0.707. Pushing the loop bandwidth above ~f_ref/10 erodes phase margin because the phase detector samples discretely at the reference rate.
• Reference spurs. Ripple at the reference frequency leaks through the loop filter onto the VCO control line, frequency-modulating the output and planting spurs at ±f_ref around the carrier. Wider loop bandwidth makes them worse. Charge-pump current mismatch and leakage are the usual culprits.
• The phase-noise crossover trade-off. Inside the loop bandwidth the output tracks (and is dominated by) reference and divider noise; outside it the VCO's own phase noise takes over. There is one loop bandwidth that minimizes total integrated jitter, where the two noise sources cross — choosing it is the heart of synthesizer design.
• Cycle slipping during acquisition. If the input steps too far for the loop bandwidth, the loop slips whole cycles before catching, lengthening lock time unpredictably. A PFD with extended range or an aided acquisition (frequency sweep, coarse-tune DAC) prevents it.
• False lock and harmonic lock. A multiplier-type phase detector can lock to a harmonic or a sideband of the intended frequency. PFDs largely eliminate this because they discriminate frequency direction.
• VCO pulling and supply sensitivity. A high K_VCO makes the loop easy to tune but couples supply and substrate noise straight into the output as phase noise. Segmenting the tuning range (a coarse band-select plus a fine varactor) keeps K_VCO low where it matters.

Common pitfalls when designing a PLL

• Setting the loop bandwidth too wide. Tempting for fast lock, but it lets reference spurs through and erodes stability. Keep ω_n ≲ f_ref/10.
• Forgetting the divider in the gain equation. The feedback divide ratio N appears in the denominator of ω_n; a synthesizer's loop dynamics change as you reprogram N across the band, so a filter tuned at one channel may be sluggish or unstable at another.
• Ignoring charge-pump leakage. In a type-2 loop, leakage on the control-voltage node forces the charge pump to correct it every reference cycle, producing reference spurs even at perfect lock.
• Treating the PLL as a continuous-time system. The phase detector samples at the reference rate; the continuous-time approximation is only valid when the loop bandwidth is well below the reference, which is the real reason behind the f_ref/10 rule.
• Optimizing only for lock time or only for jitter. They pull in opposite directions through the loop bandwidth. The right answer is the jitter-minimizing bandwidth, then accept the resulting lock time — or add aided acquisition if it is too slow.