Sigma-Delta ADC

How a sigma-delta ADC works

Most ADC architectures try to measure a voltage accurately in one shot — flash converters use a ladder of precise comparators, SAR converters use a precise capacitor DAC and a binary search. A sigma-delta converter does the opposite. It uses one crude comparator (a 1-bit quantizer that can only say "above" or "below"), runs it absurdly fast, and recovers accuracy by averaging the result over time. The accuracy lives in the timing and the digital filter, not in the analog comparator.

The analog part — the modulator — is a feedback loop with three blocks. A summing node subtracts the previous output (fed back through a 1-bit DAC) from the input. That difference (the "delta") flows into an integrator that accumulates it (the "sigma," a running sum). The integrator's output drives a comparator clocked at the oversampling rate, emitting a 1 if the accumulated value is positive and a 0 if negative. That single bit is the output, and it is also fed straight back to the summing node.

The loop is self-correcting. If the input is, say, 70% of full scale, the only way the integrator can stay bounded is for the bitstream to be 1 about 70% of the time. So the density of ones tracks the input voltage. Feed it a sine wave and the local 1-density rises and falls with the waveform. That dense, high-rate, 1-bit pulse-density stream carries the whole signal — you just have to extract it.

The digital part — the decimation filter — does the extraction. It low-pass filters the bitstream (averaging removes the high-frequency garbage) and downsamples it back to the Nyquist output rate, producing a clean multi-bit word per output sample. A cascaded-integrator-comb (CIC / sinc) filter does the cheap bulk decimation; a FIR stage flattens the passband and sets the final brick-wall response.

     x(t)        +        ___________       ____________      1-bit stream
  ----------->( Σ )----->| integrator|---->| comparator |--------+------>  to
               ^  -       |  1/(1-z^-1)|    | (quantizer)|        |     decimation
               |          |___________|     |___________|        |       filter
               |                                                 |
               |              ____________                       |
               +-------------| 1-bit  DAC |<----------------------+
                             |____________|

The governing math: oversampling and noise shaping

Two mechanisms combine to deliver the resolution. Start with plain oversampling. The total quantization noise power of an N-bit quantizer is fixed at Δ²/12 (where Δ is the LSB step), and it spreads uniformly from DC to half the sample rate. If you sample OSR times faster than Nyquist, that same noise power spreads over OSR times more bandwidth, so only 1/OSR of it lands in the band you keep. Each doubling of OSR removes 3 dB of in-band noise — worth 0.5 bit.

Oversampling alone is weak. Noise shaping is where sigma-delta earns its keep. The integrator in the loop acts as a high-pass filter for the quantization noise but is transparent to the signal. In the z-domain, an Lth-order loop applies a noise transfer function (NTF) of (1 − z⁻¹)ᴸ to the quantization error while the signal transfer function (STF) stays flat. The in-band noise is pushed toward high frequency where decimation discards it.

Quantization noise power (uniform):     e²_rms = Δ² / 12
Output noise spectral density:          Y_noise(f) = E(f) · (1 − z⁻¹)ᴸ,  z = e^{j2πf/fs}
In-band RMS noise (order L, ratio OSR):  n_rms ≈ e_rms · π^L / ( sqrt(2L+1) · OSR^{L+0.5} )

Resolution gain per octave of OSR:
   order L = 0 (plain oversample):  +0.5 bit / octave
   order L = 1:                     +1.5 bit / octave
   order L = 2:                     +2.5 bit / octave
   order L = 3:                     +3.5 bit / octave   (general:  L + 0.5)

SNR (dB) for an ideal Lth-order, 1-bit loop:
   SNR ≈ 6.02·B + 1.76  with  B = 1 + (L + 0.5)·log2(OSR) − 0.5·log2( π^{2L}/(2L+1) )
                              (the leading 1 is the 1-bit quantizer's own bit)

The signal-to-noise ratio relates to effective bits through the classic SNR = 6.02·ENOB + 1.76 dB. So if a design reaches 98 dB SNR over the audio band, that is (98 − 1.76)/6.02 ≈ 16 effective bits — from a 1-bit converter.

Worked example: a 16-bit audio modulator

Target: CD-quality audio — 96 dB SNR over a 20 kHz band, i.e. 16 effective bits, from a 1-bit quantizer. Pick a 2nd-order loop (L = 2) and find the oversampling ratio.

Output (Nyquist) rate:   fN = 48 kHz   (band edge fB = 20 kHz)
Quantizer:               1-bit, so raw SQNR ≈ 6.02·1 + 1.76 = 7.78 dB (useless alone)
Loop order:              L = 2

Use the full ideal SNR (don't forget the fixed NTF penalty):
   SNR ≈ 6.02·1 + 1.76 + (2L+1)·10·log10(OSR) − 10·log10( π^(2L)/(2L+1) )
   penalty term (L=2):  −10·log10(π⁴/5) ≈ −12.9 dB  (≈ 2.1 bits — the asymptotic
                        "+2.5 bits/octave" alone overshoots by this much)

Solve for 96 dB:        50·log10(OSR) ≈ 96 − 7.78 + 12.9 = 101  →  OSR ≈ 105
   round to a binary, standard ratio  →  OSR = 128
   check:  SNR ≈ 100 dB  →  (100 − 1.76)/6.02 ≈ 16.3 effective bits  ✓
   (OSR = 64 here gives only ~85 dB ≈ 14 bits — short of CD quality)

Modulator clock:         fs = OSR · fN = 128 × 48 kHz = 6.144 MHz
Decimation:              ÷128 back down to 48 kHz, 16-bit words

So a comparator flipping ~6 million times a second, plus a digital divide-by-128 filter, replaces a 16-bit precision DAC ladder. This is exactly the clock you see on real parts: many audio codecs run a 64× or 128× modulator at a few MHz off a 12.288 MHz master clock. (A 2nd-order loop at only 64× lands around 14 bits — to reach a true 16 bits at 64× you bump the loop order instead of the ratio.) Push the loop to 4th or 5th order and even a 64× ratio clears 110+ dB — 18 effective bits — which is why modern codecs reach 24-bit registers even though only ~21 of those bits are real.

Now the latency cost. The decimation filter needs several output periods to settle. A typical group delay of ~5 output samples at 48 kHz is about 100 µs — inaudible for playback but fatal if you tried to multiplex this converter across 8 sensor channels and read each in one cycle.

Sigma-delta vs other ADC architectures

	Sigma-delta	SAR	Flash	Pipeline	Dual-slope
Core mechanism	Oversample + noise-shape + decimate	Binary search w/ cap DAC	2ᴺ−1 parallel comparators	Cascaded low-res stages	Integrate up, integrate down, count
Resolution	16 to 24 (up to 32) bits	8 to 18 bits	4 to 8 bits	10 to 16 bits	12 to 22 bits
Speed	Low to moderate (≤ few Msps effective)	Moderate (to a few Msps)	Very high (GSps)	High (tens to 100s Msps)	Very low (a few Sps)
Latency per sample	High (many cycles)	Low (1 cycle)	Lowest (≈0)	Pipeline depth (cycles)	Very high (line-cycle)
Analog precision burden	Low (shifted to digital)	High (cap matching)	Very high (comparator matching)	Moderate per stage	Low (timing-based)
Anti-alias filter	Trivial (1st-order RC)	Sharp brick-wall needed	Sharp needed	Sharp needed	Inherent (integration)
Die area / power per bit	Small (digital scales)	Small/moderate	Large (exponential)	Moderate	Small
Typical home	Audio codecs, scales, precision DC, sensors	MCU front-ends, DAQ, multiplexed sensors	Oscilloscopes, RF, radar	Video, comms, software-defined radio	Bench DMMs, panel meters

Real-world parts and figures

Part / system	Order & bits	OSR / clock	Notes
Cirrus Logic / AKM audio codec	4th–5th order, 24-bit reg (~20 ENOB)	64× / ~3.07 MHz	Multi-bit quantizer + dither; THD+N near −100 dB
TI ADS1256 (precision DAQ)	4th-order, 24-bit	up to 30 ksps, OSR programmable	~23 noise-free bits at low data rate; strap-gauge bridges
Digital weigh scale / load cell	2nd–4th order, 24-bit (e.g. HX711)	10–80 Hz output, MHz modulator	50/60 Hz mains rejection via sinc notch placement
MEMS PDM microphone	4th-order, 1-bit PDM out	1–3.072 MHz PDM clock	Modulator only — host SoC runs the decimator
SACD / DSD audio	typ. 5th-order, 1-bit	2.8224 MHz (64 Fs)	The 1-bit stream is the stored format — never decimated
ΣΔ isolated current sense (motor drives)	2nd–3rd order, 16-bit	5–20 MHz	Bitstream crosses an isolation barrier; sinc³ filter in FPGA

Concrete numbers worth carrying: oversampling alone gives 3 dB (0.5 bit) per doubling; a 2nd-order loop gives 15 dB (2.5 bits) per doubling — a 5× better return on clock speed. A 24-bit register at 24 ENOB would imply 146 dB dynamic range, which exceeds what the analog reference and resistors can deliver, so real "24-bit" precision parts publish 19–23 noise-free bits depending on data rate. Push the data rate up and the noise-free bit count drops, because faster output means a wider decimation band and less averaging.

Design tradeoffs and failure modes

• Order vs stability. Higher loop order buys ~1 extra bit per octave per order, but single-bit loops above 2nd order can go unstable — the integrators wind up to saturation and the output sticks. Designers cap the maximum stable input (often 70–90% of full scale), use CIFB/CIFF topologies, apply the Lee criterion to limit out-of-band NTF gain (≈ 1.5), or move to a multi-bit internal quantizer.
• Idle tones (limit cycles). A low-order, 1-bit loop fed a constant DC near a simple fraction (0, ±1/2, ±1/3 FS) produces a periodic bit pattern that shows up as a spurious in-band tone — an audible whistle in audio. Cured with higher order, a multi-bit quantizer, or a small pseudo-random dither added before the comparator to randomize the pattern.
• Latency. The decimation filter has a multi-sample group delay, and the loop itself needs to settle after a step input. This makes sigma-delta a poor fit for fast multiplexed channel-hopping; SAR wins there.
• Decimation-filter passband droop. A cheap sinc/CIC decimator rolls off the top of the passband (sinc droop). A FIR compensation stage restores flatness, at the cost of more digital logic.
• Clock jitter. Because everything hinges on uniformly spaced samples, modulator-clock jitter injects noise directly. Audio-grade designs spend real effort on low-jitter master clocks (sub-picosecond) — jitter that would be invisible to a slow SAR is audible here.
• 1-bit DAC linearity. A single-bit feedback DAC has only two levels, so it is inherently perfectly linear — one of sigma-delta's superpowers. The moment you go multi-bit for stability, the feedback DAC's element mismatch reintroduces nonlinearity, which is why multi-bit loops add dynamic element matching (DEM) to scramble element usage.

Where sigma-delta ADCs are used

• Audio. Essentially every consumer audio ADC and DAC since the 1990s is sigma-delta — phone codecs, USB interfaces, studio converters. The 1-bit stream and gentle anti-alias requirement make it cheap and clean. DSD/SACD stores the raw 1-bit modulator output as the master format.
• Weigh scales and load cells. A bridge sensor outputs microvolts; a 24-bit sigma-delta with built-in gain and 50/60 Hz notch (place the sinc nulls on the mains frequency) reads grams on a 10 kg scale.
• Precision instrumentation & DC measurement. Digital multimeters, data loggers, and thermocouple/RTD front-ends use sigma-delta for its linearity and built-in mains rejection.
• MEMS microphones. A PDM mic ships only the modulator; the phone's SoC runs the decimation filter, so the wire carries a single 1-bit clocked line.
• Isolated current/voltage sensing in motor drives. The 1-bit bitstream crosses a capacitive or magnetic isolation barrier easily, and an FPGA sinc³ filter reconstructs the value on the safe side.

Common misconceptions and pitfalls

• "Oversampling removes the noise." No — total quantization noise power is conserved. Oversampling and noise shaping relocate it to high frequencies; the decimation filter is what actually discards the out-of-band portion. Skip the filter and you keep all the noise.
• "A 1-bit converter can't be accurate." The 1-bit quantizer is wildly inaccurate per sample — that is fine. Accuracy is a property of the time-averaged pulse density, recovered by the digital filter. The single bit's perfect 2-level linearity is actually an advantage.
• "24-bit means 24 real bits." The output register is 24 bits; the effective number of bits is set by SNR and is usually several bits lower, and it drops as you increase the output data rate. Always read the noise-free-bits-vs-data-rate table, not the register width.
• "Higher order is always better." Beyond 2nd order, single-bit loops risk instability and need careful NTF design; you trade resolution headroom for stability margin and design complexity.
• "You still need a sharp anti-alias filter." One of the architecture's gifts is that oversampling pushes the anti-alias corner far above the band, so a simple 1st-order RC suffices on the analog side — the brick-wall filtering happens in the digital decimator.