Thyristor (SCR)

The two-transistor model

The SCR’s strange latching behavior falls straight out of its structure. The four PNPN layers can be sliced down the middle into two interlocked bipolar transistors: a PNP (Q1) and an NPN (Q2). The collector of each drives the base of the other, so they form a positive-feedback loop.

Anode (P)──┐
           │  Q1 = PNP
        ┌──┴──┐
   N ── │     │ ── P    shared middle layers
        └──┬──┘
           │  Q2 = NPN
Cathode (N)┘     Gate ── into Q2 base

Loop condition for latch-up:
  alpha1 + alpha2 >= 1
where alpha1, alpha2 are the common-base
current gains of Q1 and Q2.

At low current the alphas are small and the loop gain is below unity, so the device blocks. Injecting a little gate current into Q2’s base raises Q2’s current; Q2’s collector feeds Q1’s base; Q1’s collector feeds back into Q2’s base. As current rises the alphas climb, and the instant alpha1 + alpha2 reaches 1 the loop becomes self-sustaining. The pair drives each other into saturation and the device snaps fully on. From then on the gate is irrelevant — the transistors keep each other on. Removing the gate signal does nothing; the latch holds.

To break the latch you must starve the loop. Drop the anode current below the holding current I_H so the alphas fall and loop gain drops back below one, and the regeneration collapses. There is no gate command that opens a standard SCR — only loss of current does.

The I–V characteristic

An SCR has three operating regions you can read straight off its anode-to-cathode characteristic:

• Reverse blocking (anode negative): like a reverse-biased diode, it blocks up to the reverse breakdown voltage V_RRM. Exceeding it is destructive.
• Forward blocking (anode positive, no gate): it still blocks, holding off the supply with only a tiny leakage current, up to the forward breakover voltage V_BO. This is the “off but ready” state.
• Forward conduction (latched): a near-vertical line at about 1–2 V drop. The device looks like a closed switch in series with a small offset voltage.

The gate current sets where on the forward axis the device breaks over. With no gate the device only fires when forward voltage reaches V_BO (hundreds to thousands of volts). Inject gate current and breakover happens at a much lower anode voltage; the more gate current, the lower the firing point. This is the entire control mechanism: a milliamp-level gate pulse decides when a kiloamp of anode current starts flowing.

Latching current vs holding current

Two thresholds govern the on-state, and confusing them causes real circuits to misfire:

• Latching current I_L — the anode current the device must reach while the gate pulse is still present for the latch to take hold. Once latched, the gate can be removed.
• Holding current I_H — the anode current below which an already-latched device drops out and turns off.

I_L is always larger than I_H, typically by a factor of 2 to 3. For a 25 A device you might see I_H ≈ 20 mA and I_L ≈ 60 mA. The consequence bites with inductive loads: when an SCR fires into an inductor, di/dt is limited, so the anode current rises slowly. A short gate pulse may end before the current ever reaches I_L, and the device quietly fails to latch. The fix is a longer gate pulse, a pulse train, or a hard gate drive that holds the gate on through the rising edge.

Phase control and the firing angle

The killer application is regulating AC power without burning it off in a resistor. On a sinusoidal line the SCR can only fire after its anode goes positive, and it commutates off automatically at the next zero crossing. By delaying the gate pulse by a firing angle α after each zero crossing, you control how much of each half cycle the load sees.

Half-wave, resistive load:

  V_avg = (V_m / 2pi) * (1 + cos alpha)

  alpha = 0     -> full conduction (max power)
  alpha = 90    -> half the available area
  alpha = 180   -> zero conduction (off)

RMS for full-wave (two SCRs, resistive):

  V_rms = V_in * sqrt( 1 - alpha/pi + sin(2 alpha)/(2 pi) )

A light dimmer works exactly this way (usually with a TRIAC for both half cycles): turn the knob and you move α from near 0 (bright) toward 180 (off). Because the device is either fully on (~1.5 V drop) or fully off, almost no power is wasted in the switch itself — a 1 kW dimmer dissipates only a few watts, versus the 250+ W a series rheostat would waste at half brightness.

The trade-off is harmonics. Chopping the sinusoid mid-cycle injects current harmonics and electrical noise back into the line. Phase-controlled drives need input filters and contribute to a poor displacement power factor, which is why large installations pair them with power-factor correction and harmonic filters.

Turn-off: natural vs forced commutation

Because the gate can’t turn the device off, turning an SCR off is its own engineering problem:

• Natural (line) commutation. In any AC circuit the current passes through zero twice per cycle. As it dips below I_H, the latch releases on its own. Free and reliable — the reason SCRs dominate AC controllers and line-commutated converters.
• Forced commutation. In a DC circuit there is no zero crossing, so you must engineer one. A pre-charged commutating capacitor is dumped across the conducting SCR to momentarily reverse-bias it and drive its current below I_H. This adds bulky capacitors and timing circuitry — one big reason fully-controllable switches (IGBTs, GTOs, power MOSFETs) displaced SCRs in DC chopper and inverter duty.

After current zero the device also needs a minimum turn-off time t_q (tens to hundreds of microseconds) to clear stored charge before forward voltage may be reapplied; reapply too soon and it re-fires spuriously. This recovery time caps the switching frequency of line converters at a few hundred hertz to low kilohertz.

SCR vs other power switches

	Thyristor (SCR)	TRIAC	GTO	IGBT	Power MOSFET
Conducts	One direction	Both directions	One direction	One direction	One direction (+ body diode)
Turn-on control	Gate pulse	Gate pulse	Gate pulse	Continuous gate voltage	Continuous gate voltage
Turn-off control	None (current zero)	None (current zero)	Negative gate pulse	Gate voltage	Gate voltage
Latching?	Yes	Yes	Yes	No	No
On-state drop	~1.5 V	~1.5 V	~2–3 V	~1.5–2.5 V	I·RDS(on)
Max ratings	~8.5 kV / 5 kA	~1.2 kV / 40 A	~6 kV / 6 kA	~6.5 kV / 3 kA	~1 kV / 100 A
Switching freq	Line (50/60 Hz–kHz)	Line	~1 kHz	~20–100 kHz	~100 kHz–MHz
Typical use	HVDC, rectifiers, soft starters	Dimmers, AC switches	Traction, high-power inverters	Motor drives, inverters	SMPS, low-voltage switching

Worked example: firing angle for a target output

A half-wave phase-controlled SCR feeds a resistive heater from a 230 V (RMS) / 50 Hz line. The peak line voltage is V_m = 230√2 ≈ 325 V. What firing angle α gives 50% of the maximum average output?

Max average (alpha = 0):
  V_avg,max = V_m / pi = 325 / 3.1416 = 103.5 V

Half-wave average vs alpha:
  V_avg = (V_m / 2pi) * (1 + cos alpha)

Target 50% of max:
  V_avg = 0.5 * 103.5 = 51.7 V

Solve:
  51.7 = (325 / 6.2832) * (1 + cos alpha)
  51.7 = 51.7 * (1 + cos alpha)
  1 + cos alpha = 1.0
  cos alpha = 0          ->  alpha = 90 degrees

Firing at the peak of each half cycle (α = 90°) delivers exactly half the maximum average voltage. To dim further toward zero you keep increasing α toward 180°; to brighten you reduce α toward 0°. The relationship is nonlinear — equal knob steps near 90° change output much faster than near the ends — which is why dimmer circuits often add a corrective taper.

Key ratings and how they bite

• V_DRM / V_RRM — peak repetitive off-state forward and reverse voltages. Pick a device rated well above the line peak plus transients; a 230 V line (325 V peak) wants at least an 800 V part.
• I_T(AV) / I_T(RMS) — average and RMS on-state current. Sized with margin and a heatsink; the ~1.5 V drop times hundreds of amps is real conduction loss.
• I²t — the fusing rating, governing how much surge energy the die survives in one cycle. It sets which series fuse can clear a fault before the SCR fails.
• di/dt — max rate of anode current rise after firing. Conduction begins near the gate and spreads across the die at finite speed; too-fast di/dt overheats the small initial conduction zone and punches through. A small series inductor limits it.
• dV/dt — max rate of forward voltage rise. Too fast and junction-capacitance displacement current self-triggers the device. An RC snubber slows the edge.
• t_q — circuit-commutated turn-off time. Reapply forward voltage before stored charge clears and the SCR re-fires uncommanded.

Common failure modes

• False dV/dt turn-on. A fast transient or a steep voltage edge across the device couples through its internal capacitance and fires it without a gate command. In a bridge this can shoot through and short the supply. Fix: RC snubber across the device and transient suppression on the line.
• Failure to latch. Gate pulse too short or too weak for an inductive load whose current never reaches I_L before the pulse ends. The device drops out at gate removal. Fix: longer gate pulse, pulse train, or higher gate drive.
• di/dt destruction. A capacitive or low-impedance load slams current through before conduction spreads across the die, overheating the local turn-on region. Fix: series di/dt inductor and a hard, fast gate drive to spread conduction quickly.
• Commutation failure. In a line-commutated converter, too small a margin angle means forward voltage reappears before t_q elapses; the device re-conducts and the converter loses control — a classic cause of HVDC inverter commutation failures during AC faults.
• Overvoltage breakover. Exceeding V_BO or V_RRM punches through the blocking junction; the device fires in the wrong place or fails short. Fix: voltage margin and metal-oxide varistor clamping.
• Thermal runaway. Leakage and on-state losses raise junction temperature, which raises leakage further. Without adequate heatsinking the junction exceeds ~125–150 °C and the device fails short. Fix: derate current with temperature and size the heatsink for worst-case duty.