MOSFET Gate Driver IC

The problem — gate capacitance vs logic pin current

A power MOSFET's gate is functionally a small capacitor of a few hundred picofarads to a few tens of nanofarads, depending on device size. The datasheet specifies total gate charge Q_g — the integrated charge needed to switch the gate-source voltage from 0 to the recommended drive level (typically 10 V for silicon, 18 V for SiC). For a representative medium-power MOSFET like Infineon's IPP60R299CFD7 (650 V, 16 A, used in switch-mode supplies), Q_g is roughly 18 nC. A bigger TO-247 device like the IXFH80N50P3 (500 V, 80 A) is 130 nC. A 1200 V SiC module like the Wolfspeed CAB011M12FM3 is closer to 400 nC.

To switch any of those gates in a useful time you need to deliver Q_g in t_rise. Express it as a current:

I_gate_avg = Q_g / t_rise

   50 nC / 20 ns  = 2.5 A average source current to switch in 20 ns
  100 nC / 50 ns  = 2.0 A average source current
  400 nC / 100 ns = 4.0 A average source current
 1000 nC / 200 ns = 5.0 A average source current

A typical microcontroller GPIO pin sources 8 to 20 milliamps. That's two orders of magnitude shy of even the smallest practical fast-switching MOSFET. Drive the gate directly from the micro and the gate-source voltage ramps over microseconds instead of nanoseconds; the device spends most of its switching time in the linear region where V × I overlap is huge; switching losses dominate; the device heats up; efficiency collapses; sometimes the MOSFET fails from thermal runaway during the slow transitions.

What the gate driver actually does

A gate driver IC is a small low-side or half-bridge power amplifier specifically designed to drive a capacitive load. The simplest single-channel non-isolated drivers (Texas Instruments UCC27511, ON Semiconductor NCP3420) are essentially a totem-pole pair of MOSFETs — one P-channel pulling up to V_DD and one N-channel pulling down to ground — with logic-level inputs, internal level shifting, and modest under-voltage lockout protection.

Simplified single-channel gate driver topology
   V_DD (12 V)
      │
      ●─────────┐
                │
              [Q_HS]   high-side MOSFET (P-ch, pulls up to V_DD)
                │
   logic ───●───●─────► OUT (gate of power MOSFET)
            │   │
            ●  [Q_LS]   low-side MOSFET (N-ch, pulls down to GND)
                │
                ●─────┐
                      │
                     GND

The logic input toggles which output device conducts. When the input goes high, Q_HS turns on and dumps current from V_DD into the load gate, charging it toward V_DD; when the input goes low, Q_LS turns on and dumps the load gate's stored charge down to ground. Both output devices are sized to handle peak currents of 4-6 A continuously through nanosecond pulse widths — the driver's die area is dominated by these big output MOSFETs.

Beyond the raw current drive, real gate drivers add a stack of protective and convenience features:

• Under-voltage lockout (UVLO). The driver refuses to operate when V_DD is below the level needed to fully enhance the power MOSFET's gate; this prevents the device from operating in its linear region during start-up or brown-out, where it would overheat.
• Independent source and sink resistance pins. Some drivers separate the source (charge) and sink (discharge) paths so the user can fit a different external resistor on each, controlling turn-on and turn-off speeds independently.
• Negative gate drive. SiC and high-dV/dt applications use -5 V or -8 V instead of 0 V for the off-state to prevent Miller-induced re-triggering.
• Desaturation (DESAT) protection. For IGBT and SiC drivers, the IC monitors V_CE during the on-state and if it remains above a threshold (indicating excessive current or a short), shuts the gate off in microseconds.
• Dead-time enforcement. Half-bridge drivers like the IR2110 or ADuM4135 take a single logic input plus a dead-time parameter and produce two non-overlapping outputs for the high- and low-side switches.

Worked example — selecting a driver for a 100 kHz buck converter

Suppose you are designing a 48 V to 12 V, 10 A buck converter running at 100 kHz switching frequency. The synchronous low-side switch is a Infineon BSC014N04LS (40 V, 100 A, Q_g = 24 nC at V_GS = 10 V). You want 20 ns rise and fall times to keep switching losses low.

Required average gate current:
  I_gate = Q_g / t_rise = 24 nC / 20 ns = 1.2 A

Required peak gate current (~ 1.7x average, Miller plateau):
  I_peak ≈ 2.0 A

Driver selection criteria:
  - peak source / sink ≥ 2 A → UCC27511 (4 A) is comfortable
  - V_DD compatibility: BSC014N04LS recommended V_GS = 10 V → V_DD = 10-12 V
  - propagation delay: keep symmetric to minimise dead-time spread

Gate resistor R_g:
  V_DD - V_GS_plateau ≈ 12 - 6 = 6 V
  R_g = (V_DD - V_GS_plateau) / I_peak = 6 / 2 = 3 Ω

Switching power loss (estimate, per transition):
  E_sw ≈ ½ · V_bus · I_load · t_rise = ½ · 48 · 10 · 20 ns = 4.8 μJ
  At 100 kHz × 2 transitions/cycle: P_sw = 4.8 μJ × 200 kHz = 0.96 W

Driver power consumption:
  P_drv = Q_g · V_DD · f_sw = 24 nC · 12 V · 100 kHz = 28.8 mW
  (negligible compared to power-stage losses)

The driver itself burns under 30 mW because gate charge is small; the MOSFET burns 1 W in switching losses. Multiply by two switches in a sync buck and you're at 2 W of switching loss in a 120 W converter — about 1.7 percent of throughput, dominated by transition energy. Slow the gate drive to 200 ns (10× slower) and switching loss rises to 20 W — 17 percent of throughput — at which point the converter no longer meets efficiency or thermal targets. The 4 A driver costs $0.50; the consequences of not using it cost the whole design.

High-side drive — bootstrap, charge pump, or isolated

Half-bridge topologies (every motor drive, every full-bridge converter, every Class-D amplifier) need to drive a high-side N-channel MOSFET whose source is connected to the floating switch-node, not to ground. The gate-source voltage of that MOSFET still needs to swing 10-15 V positive — but referenced to a node that swings up to V_bus. Three solutions dominate.

Approach	How it works	Cost	Limits	Used in
Bootstrap diode + capacitor	Cap charges from V_DD through diode when low-side is on; floats up to V_bus + 12 V when high-side is on; supplies gate drive	Cheapest — one diode + one cap	High-side must turn off periodically to refresh; not for 100% duty cycle	IR2110-class half-bridge drivers, motor drives, buck/boost converters
Charge pump	Internal switched-capacitor doubler runs continuously from V_DD, generating the floating rail	Slightly more silicon area	Limited output current; works for low-current MOSFETs only	Automotive smart-switches, low-current high-side LED drivers
Isolated gate driver	Small transformer / optical / capacitive coupler transmits signal; separate floating bias supply	Most expensive — needs isolation barrier + auxiliary supply	Bias supply must be designed	SiC traction inverters, MV converters, solar string inverters at 1500 V

Bootstrap is the workhorse for sub-600 V designs because it's nearly free. Isolated drivers dominate above 600 V where the dV/dt rates (10-100 V/ns for SiC) couple destructive currents through any non-isolated common path. The breakpoint is roughly the same boundary at which silicon MOSFETs give way to SiC: 600 V and above. Below it, bootstrap wins on cost; above it, isolation is mandatory for reliability.

The Miller plateau — where most of the gate current goes

The MOSFET's gate-source voltage V_GS does not rise smoothly during turn-on. The waveform has three regions:

  V_GS
    ↑       ╭───────────  V_DD (12 V)
            │
  V_GS,plat │── flat region (Miller plateau) ──────
            │
  V_th      │
            │ ╱
    0 ──────╯─────────────────────────────────────► t

  Phase 1: V_GS rises from 0 to V_th — drain current is zero
  Phase 2: V_GS rises from V_th to V_GS,plat — drain current rises to I_load
  Phase 3 (Miller plateau): V_GS held flat — V_DS collapses from V_bus to V_DS(on)
  Phase 4: V_GS rises from V_GS,plat to V_DD — channel fully enhanced

The Miller plateau is where most of the switching energy is dissipated. During phases 1-2 the drain voltage is still high and rising current overlaps with that voltage. During phase 3 the drain voltage is collapsing and the energy ½·C_GD·V_bus² is being dumped through the channel. Once phase 3 ends and the drain has reached V_DS(on), the device is fully on and additional gate charge in phase 4 just enhances the channel further.

The driver's peak current is needed during phase 3 because the driver is supplying current entirely into the gate-drain capacitance C_GD; V_GS does not rise because the current is going into C_GD instead. Shortening phase 3 — by increasing the driver's peak current and decreasing R_g — collapses V_DS faster, cuts switching losses, but raises dV/dt rates that can cause EMI and Miller-induced cross-conduction.

Driver IC families — pick by topology and voltage class

Driver	Topology	Peak I	V_max	Isolation	Typical use
TI UCC27511	Single low-side	4 A	18 V V_DD	None	Sync buck, low-side switches under 100 V
Microchip TC4452	Single low-side	13 A	18 V	None	Large MOSFETs, IGBT modules at low voltage
Infineon IR2110	Half-bridge bootstrap	2 A	600 V offset	None (bootstrap)	Classic motor drives, audio amps
Silicon Labs Si8261	Half-bridge bootstrap	4 A	650 V offset	None (bootstrap)	Modern motor drives, improved noise immunity
ADI ADuM4135	Isolated single	4 A	1200 V isolation	iCoupler (magnetic)	SiC/IGBT modules in solar inverters, EV inverters
Skyworks Si8285	Isolated single	4 A	5 kV isolation	Capacitive	SiC modules, high-CMTI applications (100 V/ns)
TI DRV8350	3-phase bridge bootstrap	1 A	100 V	None (bootstrap)	Small BLDC/PMSM drives, e-bikes, drones
ON NCD57252	Isolated SiC driver	15 A	1700 V isolation	Optical	EV traction inverters, large solar strings

Pitfalls and failure modes

• Missing local decoupling. The driver's instantaneous current spikes — 4-6 A in 20 ns — must come from a low-ESR capacitor right at the V_DD pin. A 100 nF X7R ceramic with under 1 cm of trace inductance is the minimum; many designs add a parallel 1-10 μF. Without it, V_DD sags below UVLO mid-transition and the driver oscillates, frying the output stage.
• No gate resistor. Connecting driver output directly to the MOSFET gate makes the gate-source loop a high-Q LC tank — the gate capacitance plus the trace + package inductance can oscillate at 50-200 MHz. Output bounces, gate-oxide voltage spikes past V_GS,max (often only ±20 V) and the device dies. Always use a series gate resistor (1-22 Ω typical).
• Bootstrap diode reverse-recovery. The bootstrap diode must recover quickly when the high-side switch turns on, or it back-pumps current into the V_DD rail at the switching frequency. Choose ultra-fast (50 ns t_rr) or Schottky (zero t_rr) diodes for high-frequency designs.
• Insufficient dead time. If high-side and low-side switches in a half-bridge overlap by even 50 ns during the transition, shoot-through current spikes destroy the FETs. Dead time of 100-500 ns is the standard; verify with current-shunt scope captures during commissioning.
• Common-mode current through isolated drivers. A fast dV/dt on the switch-node forces displacement current through the isolation barrier's parasitic capacitance. If CMTI (common-mode transient immunity) is too low (under 30-50 V/ns for SiC), the driver latches up. Choose drivers rated for the bridge's worst-case dV/dt.
• Trace inductance in the gate-loop. The gate-source loop carries 4-6 A peak in 20 ns — di/dt up to 300 A/μs. Any trace inductance L in this loop drops V = L · di/dt that subtracts from V_GS; 10 nH causes 3 V of inductive drop, which can drop the gate below threshold during the rising edge. Place the driver IC within 5-10 mm of the MOSFET and route the gate loop as a tight pair.

A short history — from discrete totem-poles to integrated SiC drivers

Through the 1970s and into the early 1980s power MOSFETs were driven by discrete totem-pole pairs of bipolar transistors — typically a 2N3906 / 2N3904 complementary pair with a small driver transistor in front. By the late 1980s the first integrated gate drivers appeared from International Rectifier (the IR2110 family in 1989, still in production), Linear Technology, and Texas Instruments. Each generation added more features: under-voltage lockout, current sourcing capability, then desaturation protection in the IGBT era of the 1990s.

The SiC revolution forced another redesign. Silicon MOSFETs are tolerant of slow gate drive and modest dV/dt; SiC MOSFETs need much higher dV/dt (10-100 V/ns) to cash in their low switching losses, and that demands gate drivers with reinforced isolation, very high CMTI (50 V/ns or more), and negative off-state drive. Companies like Analog Devices (ADuM4135), Skyworks/Silicon Labs (Si8285), Texas Instruments (UCC53xx), and ON Semiconductor (NCD57252) shipped dedicated SiC gate drivers between 2017 and 2022. GaN HEMTs need even faster gate drive at lower voltage (5-6 V instead of 12 V) and slightly different bias; another driver family has emerged for that (LMG1020, UCC27282).