Zero-Voltage Switching (ZVS): Soft-Switching to Kill Turn-On Loss

What ZVS Is and Where It Lives

Zero-voltage switching is a turn-on soft-switching method: the control forces the drain-to-source voltage of a switch to (or near) zero before the gate command arrives, so the transistor turns on into a collapsed voltage. Contrast this with hard switching, where the device turns on while its full off-state voltage (say 400 V) is still present, discharging its own output capacitance C_oss through the channel as heat.

ZVS is the backbone of nearly every high-density isolated converter shipping today:

• LLC resonant converters — the standard for server, telecom, and USB-C PD supplies; primary MOSFETs achieve ZVS across the full load range using the transformer magnetizing current.
• Phase-shifted full bridge (PSFB) — 500 W–5 kW EV chargers and telecom rectifiers, using leakage inductance to charge/discharge the bridge legs.
• Active-clamp flyback and class-E/class-D amplifiers — laptop adapters and RF/wireless-power stages running at 1–13.56 MHz.

Wherever switching frequency is pushed up to shrink magnetics, ZVS is what keeps the transistors from melting.

The Mechanism: Resonant Transition During Dead Time

ZVS exploits the dead time — the brief interval when both switches in a half-bridge leg are off. During that window the switch-node capacitance (the two devices' C_oss plus stray capacitance, call it C) resonates with an inductor L (leakage inductance in a PSFB, magnetizing inductance in an LLC).

The sequence for one leg:

• The conducting switch turns off. Inductor current keeps flowing and must go somewhere — it charges the just-opened switch's C_oss and discharges its complement's C_oss.
• The switch-node voltage swings from one rail toward the other along a resonant arc, period T_res = 2π·√(LC). The worst-case transition time is a quarter period, T_res/4.
• When the node reaches the opposite rail, the incoming switch's body diode begins to conduct, clamping V_DS ≈ 0 (about −0.7 V).
• The gate is turned on now, into that zero-voltage clamp. No CV², no overlap loss, and the body diode's charge is swept out under ZVS rather than as reverse recovery.

The whole trick is timing the gate to arrive during that clamp — and having enough inductor energy to complete the swing.

Key Quantities and a Worked Example

The governing condition is an energy inequality: the inductive energy must exceed the capacitive energy needed to slew the node across the bus.

• ZVS condition: ½·L·I² ≥ ½·C_eq·V_bus² (a factor of 2·C_oss because two devices swing; use the charge-equivalent C_oss(er), not the small-signal value).
• Transition time: t_ZVS ≈ (π/2)·√(L·C) at worst case; more precisely t = C·V_bus / I for a near-constant current source.
• Dead time rule: t_dead must bracket t_ZVS — long enough for the swing, short enough not to lose the body-diode clamp.

Worked example (PSFB leg): V_bus = 400 V, two MOSFETs with C_oss(er) = 150 pF each (C = 300 pF total), leakage L = 6 µH. To complete the swing you need I ≥ V_bus·√(C/L) = 400·√(300 pF / 6 µH) = 400 × 7.07 mA/V-scale ≈ 2.83 A. Transition time ≈ C·V/I = 300 pF × 400 V / 2.83 A ≈ 42 ns, so set dead time ~50–80 ns. Below ~2.83 A of leg current (i.e., at light load) the leg loses ZVS — the classic PSFB failure at low load.

Designing and Operating for ZVS in Practice

Getting ZVS in the lab, across line and load, comes down to a handful of levers:

• Choose low-C_oss devices. Every picofarad of switch-node capacitance is energy the inductor must supply. Super-junction MOSFETs and especially GaN HEMTs (which have no body-diode reverse recovery and low, flat C_oss) are the reason MHz ZVS is practical.
• Size the resonant/leakage inductance. More L means ZVS holds to lighter loads, but too much L costs duty-cycle (PSFB) or raises the LLC's magnetizing current and conduction loss. It's a trade, not a free win.
• Tune dead time to the operating point. Because required time scales with C·V/I, many controllers (e.g., adaptive dead-time schemes) shorten dead time at heavy load and lengthen it at light load.
• Keep the LLC above resonance (f_sw ≥ f₀). Operating in the inductive region guarantees the tank current lags voltage, which is exactly the condition that guarantees primary-side ZVS.

Verify with a scope: watch V_DS hit zero before the gate rises. If the gate edge sits on a nonzero V_DS shelf, you're still hard-switching.

ZVS vs ZCS and the Hard-Switched Baseline

ZVS has a mirror-image sibling, zero-current switching (ZCS), and the two solve different problems:

• ZVS zeroes voltage at turn-on. It's ideal for majority-carrier, capacitance-dominated devices — MOSFETs and GaN — where the pain is CV² turn-on loss and body-diode reverse recovery. Turn-off is also softened because C_oss slows the voltage rise.
• ZCS zeroes current at turn-off. It suits minority-carrier devices — IGBTs and thyristors — whose dominant loss is the current tail during turn-off; forcing i→0 first removes the overlap.

Against a hard-switched baseline, both cut switching loss, but ZVS is generally preferred at high frequency because MOSFET/GaN switching loss is turn-on-and-Coss-dominated. Related soft-switching families include quasi-resonant (valley switching) flybacks, which achieve partial ZVS by turning on at the C_oss ringing minimum, and zero-voltage-transition (ZVT) cells that add an auxiliary switch and inductor to a hard PWM converter to create a ZVS window without making the whole converter resonant.

Failure Modes, Trade-offs, and Why It Matters

ZVS is powerful but not free, and it fails in characteristic ways:

• Loss of ZVS at light load. The inductor current drops below I_min = V_bus·√(C/L), the node never reaches the far rail, and the switch turns on into a partial (or full) hard edge — an efficiency cliff and an EMI spike exactly when the converter should be most efficient. PSFB and LLC both suffer this; fixes include burst mode, a shunt magnetizing path, or auxiliary ZVS circuits.
• Dead-time too long. The body diode conducts far longer than needed, adding conduction loss (and, in silicon MOSFETs, reverse-recovery charge if the gate arrives after the diode is already conducting hard).
• Dead-time too short / mis-tuned. Turn-on lands on a nonzero V_DS shelf — you paid for the resonant components and still hard-switch.
• Circulating-current penalty. The magnetizing/leakage current that enables ZVS also circulates as conduction loss; over-provisioning it to guarantee light-load ZVS wastes copper.

The significance is enormous: ZVS is what lets a 3 kW server rectifier hit 97–98% efficiency and shrink its transformer by pushing to 250 kHz–1 MHz. Without soft switching, high-frequency, high-density power conversion simply does not close on thermals.

ZVS vs ZCS vs hard switching — what each addresses and where it fits

Property	Hard switching	ZVS (zero-voltage)	ZCS (zero-current)
Loss eliminated	None (both edges lossy)	Turn-ON: CV² + reverse-recovery	Turn-OFF: current tail overlap
Best device fit	Any (low freq)	MOSFET / GaN HEMT (capacitive)	IGBT / thyristor (tail current)
Energy source for soft edge	—	½·L·I² in resonant/leakage inductor	Resonant tank forces i→0
Main parasitic tamed	—	Coss (output capacitance)	Reverse-recovery / tail charge
Typical topology	Buck, hard flyback	LLC, phase-shifted full bridge	Series-resonant with SCR/IGBT
Frequency sweet spot	< ~150 kHz	300 kHz – several MHz	Tens–hundreds of kHz