Phase-Shifted Full-Bridge Converter: Sliding the Diagonal for ZVS

What it is and where it's used

The phase-shifted full-bridge converter is an isolated, buck-derived DC-DC converter built from a classic four-switch H-bridge driving the primary of a high-frequency transformer, with a rectifier and output LC filter on the secondary. What sets it apart is the control law: rather than chopping the pulse width, each of the two bridge legs runs its own half-bridge at a fixed 50% duty cycle, and the converter regulates by shifting the phase of one leg (the "lagging" leg) relative to the other (the "leading" leg). The temporal overlap of the two diagonals defines how long the transformer sees full input voltage, i.e., the effective duty cycle.

• Telecom & server power — 48 V and 12 V bus converters from 500 W to several kW.
• EV and battery chargers — the isolated intermediate stage after a PFC front-end.
• Industrial & welding supplies, plating rectifiers — where high current at moderate voltage is needed.
• Aerospace / high-voltage supplies — the original Virginia Tech 2 kW prototype targeted high-voltage output.

Its sweet spot is roughly 500 W–5 kW at 50–200 kHz, where soft switching pays for the extra control complexity.

How it works: sliding the diagonal for ZVS

Label the legs A (Q1 top, Q2 bottom) and B (Q3 top, Q4 bottom). Each leg outputs a 50% square wave. When Q1 and Q4 are on, the transformer sees +Vin; when Q2 and Q3 are on, it sees −Vin. The phase shift φ controls the fraction of the period during which a diagonal pair (Q1+Q4 or Q2+Q3) overlaps — that overlap is the power-delivery interval. φ = 180° gives maximum output; φ → 0° gives zero.

The magic happens in the dead-time transitions. Just before a switch turns on, its complementary switch has turned off, leaving a leg node floating. The primary current — carried by the resonant inductance Lr (transformer leakage plus an added inductor) — flows into the parasitic output capacitances (Coss) of that leg. This forms an LC resonant tank: Lr and the two Coss ring together, swinging the node from one rail to the other. If the current is large enough, the node reaches the opposite rail and the body diode conducts before the gate signal arrives, so the MOSFET turns on at zero drain-source voltage. Switching loss ½·Coss·Vin²·f collapses toward zero.

• Leading leg — commutates with the full reflected output-inductor current; ZVS is easy and holds down to light load.
• Lagging leg — commutates using only the energy in Lr; ZVS is lost first as load drops.

Key quantities and a worked example

The governing ZVS energy condition is that the inductive energy available at the transition must exceed the (dis)charge energy of the two leg capacitances plus the transformer winding capacitance:

½·Lr·Ip² ≥ 2·Coss·Vin² (approximately, with a factor often written as 4/3·Coss·Vin² to account for the nonlinear Coss(V)). Here Lr = resonant inductance (H), Ip = primary current at the transition (A), Coss = MOSFET output capacitance (F), Vin = bus voltage (V).

A second key relation is duty-cycle loss, the price of Lr: while Lr slews the primary current from +Ip to −Ip, no power reaches the secondary. Approximately ΔD ≈ (4·Lr·Io·N) / (Vin·Ts), where Io is output current, N the turns ratio, and Ts the switching period.

Example: Vin = 400 V, Coss = 300 pF per FET, fsw = 100 kHz. To achieve ZVS at Ip = 6 A: Lr ≥ 2·Coss·Vin² / Ip² = 2·(300 pF)·(400 V)² / 36 ≈ 2.7 µH. Dead time must cover a quarter resonant period: td ≈ (π/2)·√(Lr·2Coss) ≈ (π/2)·√(2.7 µH · 600 pF) ≈ 63 ns.

Designing and operating one in practice

Design is a balancing act around a single component — the resonant inductance Lr:

• Size Lr for the lightest load needing ZVS. More Lr extends the ZVS load range but increases duty-cycle loss and circulating current, hurting full-load efficiency. Many designs accept losing lagging-leg ZVS below ~30–40% load.
• Set the dead time to a quarter of the resonant period (√(Lr·Ceq) scale, tens of ns). Too short and the node never reaches the rail (hard switching); too long and the node rings back, re-charging Coss.
• Add secondary clamps or a saturable inductor to tame the notorious rectifier voltage ringing caused by Lr resonating with the diode junction capacitance — this ringing routinely doubles the rectifier voltage stress.
• Use current-mode or peak-current control to counter the flux-walking / transformer saturation risk from volt-second imbalance between the two half-cycles.
• Add synchronous rectification on the secondary for low-voltage/high-current outputs to recover diode conduction loss.

Controllers such as the TI UCC28950/51 and equivalent parts from Infineon and onsemi automate the phase-shift PWM, adaptive dead time, and synchronous-rectifier timing.

How it compares to the alternatives

Against a hard-switched full-bridge, the PSFB uses the identical power stage but adds soft switching for free (just control + a small inductor), typically lifting peak efficiency from ~91% to ~95% and slashing EMI — decisive above 50 kHz.

Against the LLC resonant converter, the trade is regulation versus peak efficiency. LLC achieves ZVS on the primary and ZCS on the secondary, reaching 97–98%, but it regulates by frequency and is happiest at a fixed input voltage; wide-Vin operation forces a large frequency swing and magnetics compromise. The PSFB regulates by phase shift at fixed frequency, so it handles wide input range and wide load range more gracefully — the common choice when the front-end voltage varies (e.g., after hold-up on a PFC bus).

• vs. active-clamp forward — the forward is simpler and cheaper but single-ended, using the core in one quadrant; PSFB's push-pull core use doubles usable power for the same core.
• vs. two-transistor forward — that topology is rugged and cheap but hard-switched and practically capped near 500 W.

Failure modes, trade-offs, and significance

The PSFB's elegance hides three recurring headaches:

• Loss of ZVS at light load. When Ip drops, the ZVS inequality fails on the lagging leg first; switching becomes hard, efficiency dips, and EMI spikes exactly where you wanted quiet operation. Mitigations include a magnetizing-current boost, a small saturating inductor, or burst/skip modes.
• Secondary rectifier ringing and overvoltage. Lr resonating with rectifier junction capacitance produces oscillations that can double diode voltage stress; RC/RCD snubbers or active clamps cost efficiency to keep peaks within the diode rating.
• Transformer flux walking / saturation. Any duty-cycle asymmetry between half-cycles biases the flux and can drive the core into saturation, producing runaway current and switch failure — hence current-mode control and DC-blocking capacitors.

The core trade-off is permanent: more resonant inductance buys a wider ZVS range but steals duty cycle and adds circulating loss. Since Sabaté, Vlatković, Ridley, Lee and Cho formalized it at IEEE APEC 1990, the PSFB has remained the default high-power isolated topology precisely because it retrofits soft switching onto a familiar, robust bridge with only a phase knob and a small inductor.

PSFB versus common isolated DC-DC alternatives at ~1–3 kW

Topology	Switching	Primary switches	Typical peak efficiency	Best fit / limitation
Hard-switched full-bridge PWM	Hard	4	90–93%	Simple; high switching loss & EMI, limited above ~50 kHz
Phase-shifted full-bridge (ZVS)	Soft (ZVS)	4	94–96%	Loses ZVS at light load; duty-cycle loss from Lr
LLC resonant half/full-bridge	Soft (ZVS + ZCS)	2–4	96–98%	Excellent at fixed ratio; poor wide-Vin regulation
Two-transistor forward	Hard	2	88–91%	Cheap, rugged; ≤~500 W, no ZVS
Active-clamp forward	Soft (ZVS on one switch)	2	91–94%	Single-ended; core reset limits power to ~1 kW