LLC Resonant Converter

Why a resonant converter at all

Every hard-switched converter — buck, boost, flyback, forward — has the same fundamental loss. The FET turns on while V_DS is still non-zero and turns off while current is still flowing. Each transition burns an energy proportional to V_DS · I_D · t_trans, and this loss multiplies with frequency. Push a 90 %-efficient forward converter from 100 kHz to 500 kHz and your switching loss quintuples while your useful output power stays the same. By 1 MHz the forward converter has fallen below 80 % efficiency.

The resonant converter rearranges the topology so that the FET turns on at exactly V_DS = 0 (zero-voltage switching, ZVS) and turns off at near zero current (near-ZCS). The switch transitions cost essentially no energy — only the bias current for the gate driver. You can push the frequency from 100 kHz to 500 kHz without losing efficiency, which shrinks the magnetics 5× and yields 96–97 % efficient converters at server PSU power.

The price is a more complex topology, more parts, more careful design, and a non-trivial small-signal model. But for any application above 200 W where efficiency matters, those costs are easily paid. By 2015, essentially every server PSU above 500 W used an LLC stage. By 2020, every 100 W USB-PD charger above $30 retail price contained an LLC.

The half-bridge LLC topology

                      L_r                       N_p     N_s
   V_in ●────[HS FET]──UUUU──┬──══════════──┬───●     ●───┬── D1 ──┬── V_out
                              │              │   │     │   │        │
                              │             ─┴─  │     │   │       ═ C_out  ⏚ load
                              │             ───  ●     ●   │
                              │              │   │     │   │
                              │             [L_m magnetising
                              │              inductance]    └── D2 ──┤
                              │              │   │     │            │
                              │              │   │     │            │
       ●────[LS FET]──────────┴──────────────┴───┘     └────────────┴── GND_sec
       Primary GND

   HS, LS = half-bridge FETs (50% duty each, complementary)
   L_r    = series resonant inductor (often integrated as transformer leakage)
   C_r    = series resonant capacitor
   L_m    = transformer magnetising inductance (parallel resonant element)
   D1, D2 = synchronous rectifier on secondary (or Schottky diodes)
   C_out  = output capacitor

The half-bridge drives a chopped 50 %-duty AC waveform onto the LLC tank. The tank — a series resonant L_r-C_r in parallel with the transformer's magnetising inductance L_m — converts that square wave into a sinusoidal current. The current flows through the transformer primary, is reflected to the secondary, rectified by a full-wave or centre-tapped rectifier, and delivered to the load. The half-bridge frequency f_sw is modulated to regulate V_out.

Two resonant frequencies, two operating regions

The LLC tank has two natural resonances:

f_r1 = 1 / (2π · √(L_r · C_r))        primary resonance
f_r2 = 1 / (2π · √((L_r + L_m) · C_r)) secondary resonance, lower than f_r1

Between f_r2 and f_r1, the converter operates in step-up mode: the tank's gain rises above unity, so V_out can exceed V_in · N_s/(2·N_p). Above f_r1, the converter operates in step-down mode: tank gain falls below unity. At exactly f_r1, the gain is 1 — primary current is purely sinusoidal in phase with the half-bridge voltage, and the transformer carries only load current (magnetising current is zero at this point). This is the optimum operating frequency, the "sweet spot" where efficiency peaks.

The third operating region — below f_r2 — is the capacitive region, where the tank impedance becomes capacitive and the converter loses ZVS. Designs always keep f_sw above f_r2 (typically a 10 % margin) to maintain soft switching across the full operating range.

How zero-voltage switching actually works

Imagine the half-bridge just before the high-side FET turns off. Primary current is flowing through HS into the tank — say +5 A. The bridge node is at V_in. HS turns off; for a brief dead-time both FETs are off. But the tank current cannot stop instantly (inductors), so it continues flowing the same direction (+5 A) — now sourced from the output capacitance of both FETs and the body diode of LS. The combined output capacitance discharges, and the bridge-node voltage falls.

If the design is correct (enough magnetising current circulating to fully discharge the node capacitance during dead-time), the bridge node reaches 0 V before LS turns on. At that instant, V_DS of LS is exactly zero — turn on costs no switching energy. The body diode is already conducting (taking over the inductor current naturally), so we just gate LS on and let it conduct losslessly.

The same trick happens on the other half cycle: LS turns off, magnetising current pulls the bridge node up to V_in, and HS turns on at V_DS = 0. Both FETs in the half-bridge achieve ZVS every cycle. The switching loss in the FETs is essentially zero — only gate-driving loss remains, which scales with f_sw but is typically under 1 W per FET.

Worked example: 400 V bus → 12 V / 80 A server PSU

Design a 960 W LLC stage for a 1 kW Titanium-class server PSU: V_in = 400 V (PFC output), V_out = 12 V at 80 A, target efficiency 97 % at full load and 95 % at 10 % load, f_r1 = 120 kHz.

Resonant tank. Choose L_r = 30 µH and C_r = 58 nF, giving f_r1 = 1/(2π·√(30µ·58n)) ≈ 120 kHz. Magnetising inductance L_m = 5·L_r = 150 µH (typical ratio for good ZVS range), so f_r2 = 1/(2π·√(180µ·58n)) ≈ 49 kHz.

Turns ratio. At resonance, the tank gain is 1, so V_in / 2 · (N_s/N_p) = V_out. Solving:

N_s / N_p = 2 · V_out / V_in = 2 · 12 / 400 = 0.06

Round to N_p = 16, N_s = 1 (with centre tap so the secondary is 1-0-1).
At resonance: V_out = (400/2) · (1/16) = 12.5 V — close enough; full-frequency-range trim achieves precise regulation.

Operating frequency range. At minimum input (low-line: 360 V after PFC ripple), f_sw drops below f_r1 to raise gain — typically reaching 80 kHz. At maximum input (high-line: 410 V), f_sw rises above f_r1 to reduce gain — typically reaching 160 kHz. Most operation sits at or just above f_r1 = 120 kHz.

Primary FETs. 500 V / 30 mΩ SiC MOSFETs (e.g. Wolfspeed C3M0030090K). At full load primary RMS current ≈ 4 A; conduction loss = 4² · 0.03 · 2 FETs · 0.5 (duty) = 0.5 W total. Switching loss ≈ 0 (ZVS).

Secondary rectifier. Synchronous-rectifier FETs (60 V / 1.5 mΩ, e.g. EPC2024). At 80 A peak per FET: conduction loss = 80² · 0.0015 · 2 FETs · 0.5 = 9.6 W. This dominates the loss budget.

Magnetics. Transformer + L_r integrated on a single core (the L_r is realised by the transformer's leakage inductance — careful interleaved winding sets the leakage to exactly 30 µH ± 10 %). PQ35 core, copper litz wire. Core loss + copper loss ≈ 4 W.

Output capacitor. Low-ESR polymer caps. 2× 470 µF in parallel handles the rectified ripple at 240 kHz (twice f_sw).

Total loss budget. Primary FETs 0.5 W + SR FETs 9.6 W + magnetics 4 W + control + miscellaneous 2 W = 16 W on 960 W output. Efficiency = 960 / 976 = 98.4 % at full load. At 10 % load, total loss drops to ~3 W on 96 W out — 97 % efficient even at light load.

LLC compared to its cousins

Topology	Switching	Peak efficiency	Efficiency @ 10% load	Magnetics	Typical f_sw	Power range
Single-switch forward	Hard	88–90 %	70–75 %	1 transformer + 1 inductor	50–200 kHz	50–500 W
Two-switch forward	Hard	89–92 %	72–78 %	1 transformer + 1 inductor	100–300 kHz	100 W–1 kW
Active-clamp forward	Partial ZVS	92–94 %	80–85 %	1 transformer + 1 inductor	100–500 kHz	100–500 W
Phase-shifted full bridge	ZVS	94–96 %	82–87 %	1 transformer + 1 inductor	50–200 kHz	500 W – 3 kW
LLC half-bridge	ZVS + ZCS	96–97 %	93–95 %	1 transformer (integrated L_r)	80–500 kHz	100 W – 3 kW
LLC full-bridge	ZVS + ZCS	96–97 %	93–95 %	1 transformer (integrated L_r)	80–500 kHz	1 – 10 kW
Phase-shifted LLC	ZVS + ZCS	97–98 %	95 %+	1 transformer (integrated L_r)	80–500 kHz	1 – 50 kW

The LLC wins decisively on light-load efficiency — the metric that matters most for 80-Plus Titanium server PSUs (which must hit ≥94 % at 10 % load) and for any battery-powered or stand-by-heavy application. Peak efficiency is also higher, by 2–3 percentage points compared to phase-shifted full bridge.

Where LLC converters show up

• Server PSUs (80-Plus Titanium). Every server PSU above 500 W with Titanium certification (≥94 % at 10 %, ≥96 % at 50 %, ≥94 % at 100 %) uses an LLC DC-DC stage. Vendors: Delta Electronics, Liteon, FSP, Acbel, Murata. The PSUs inside hyperscale data centres (Google's Open Compute, Microsoft Azure, AWS) all use LLC architectures.
• High-end USB-PD chargers. Above 65 W or 100 W (USB-PD 3.1 EPR), the topology of choice is LLC. Anker GaNPrime 200W, Belkin BoostCharge Pro 140W, Apple 140W MacBook charger — all built on LLC stages with GaN switches.
• Telecom rectifiers above 1 kW. Eltek Flatpack S, Delta NPS, and Vertiv NetSure rectifiers use full-bridge LLC stages converting 400 V PFC bus to 48 V at 2–3 kW per rectifier module.
• Television and monitor PSUs above 200 W. Modern OLED TV PSUs (LG, Samsung, Sony — 200 W+) commonly use LLC as the main DC-DC stage. The architecture provides quiet operation (the resonant tank lacks the audible buzz of hysteretic-mode converters) and tight regulation across wide load swings between picture modes.
• EV onboard chargers (3.3–22 kW). Higher-power onboard chargers use phase-shifted full-bridge LLC stages to convert PFC bus voltage to traction-battery voltage with high efficiency over wide battery-voltage ranges. Tesla, BMW, Hyundai/Kia OBCs.
• DC fast chargers for EVs (50–350 kW). Modular DC fast chargers use stacked LLC stages on the secondary side of an isolation transformer. The architecture's wide-output-range capability is essential for charging batteries from 200 V to 800 V.
• Solar inverters and battery storage systems. Battery-stage isolation in residential and commercial storage systems (Tesla Powerwall, Enphase IQ Battery, BYD Battery-Box) uses LLC variants for the DC-DC isolation between battery and bus.

Where the 3–4 % efficiency loss comes from

• Primary FET conduction. Even with ZVS eliminating switching loss, primary current still flows through R_DS(on). The conduction is small (a couple of amps RMS at 1 kW) and SiC MOSFETs give 30 mΩ at 500 V class — typical 0.5–1 W total in the primary FETs.
• Secondary rectifier conduction. Synchronous-rectifier FETs at 100 A handle most of the loss budget. With 1–2 mΩ FETs the conduction loss is 5–15 W in a 1 kW design. This is why the LLC's secondary side gets the biggest, most expensive parts.
• Magnetics. Transformer copper loss + core loss is typically 3–6 W. Litz wire and PQ-shape ferrite cores are standard.
• Resonant capacitor. C_r carries the full primary current at the resonant frequency. ESR loss is typically 1–2 W; use polypropylene or low-ESR ceramic. RMS-current rating is critical.
• Gate-driving loss. Q_g · V_drive · 2 · f_sw per FET. At 100 nC × 12 V × 2 × 100 kHz = 0.24 W per FET — small but accumulates with parallel FETs.
• Controller + bias. The LLC controller IC plus its bias supply consumes 0.5–1 W independent of load.

Most of the loss is conduction-dominated and doesn't scale with frequency — exactly why LLC converters can run at high frequency (small magnetics) without an efficiency penalty.

Common design pitfalls

• Losing ZVS at light load. ZVS requires enough magnetising current to fully discharge the FET output capacitance during dead-time. At very light load, the dynamics shift and magnetising current can fall short, forcing hard switching with audible buzz and rapid efficiency collapse. Burst-mode operation (skipping cycles at light load) preserves ZVS.
• Operating in the capacitive region. Below f_r2 (and the load- and gain-dependent ZVS boundary), the tank impedance becomes capacitive and the FET turns on into a charged-up V_DS — destructive shoot-through current. Designers must verify ZVS across all V_in, load, and temperature corners.
• Magnetising-current asymmetry. Slight asymmetry in dead-time, FET parameters, or magnetising flux can cause the resonant capacitor to develop a DC bias — pulling the operating point away from intended frequency. A start-up DC-balance circuit and dead-time precision (±2 ns) are essential.
• Insufficient L_m for ZVS range. Choosing L_m too small (relative to L_r) extends the ZVS region but raises circulating current and conduction loss. Choosing L_m too large reduces conduction loss but shrinks the ZVS region. The L_m / L_r ratio (typically 4–10) is one of the central design knobs.
• Resonant capacitor RMS overload. C_r carries the full primary current at f_sw. A 58 nF cap rated for 1 A_RMS will catastrophically fail at 4 A_RMS. Choose polypropylene film capacitors rated to 2× the operating RMS current with a margin.
• Synchronous-rectifier gating mismatch. The secondary SR FETs must turn off exactly at the zero-crossing of the rectifier current — too early and the body diode conducts (loss), too late and current reverses (catastrophic shoot-through). Adaptive SR controllers (NXP NCP4304, ON Semi NCP4308) handle this; manual SR designs are notoriously fragile.
• Start-up sequencing. At startup the resonant capacitor begins uncharged; if the half-bridge starts at high frequency (low gain), the tank cannot deliver power and the controller's startup loop fails. A burst-mode startup or frequency-foldback algorithm is required.

Historical context

The LLC topology has roots in series-parallel resonant converters of the 1980s (early papers by Steigerwald at GE and Erickson at Colorado). The combination of series resonant tank, parallel magnetising element, and frequency-modulation control was formalised in publications from Yang, Lee, and Liang at Virginia Tech CPES in the late 1990s. The modern controller-IC revolution (ICE2HS01G from Infineon in 2009, NCP1399 from ON Semi in 2010) commoditised the design and pushed LLC into mass-market server PSUs.

The 2010s saw LLC become the default in server PSUs as 80-Plus efficiency tiers rose to Titanium (96 % peak, 94 % at 10 %). The 2020s added GaN and SiC switches, enabling higher-frequency designs and the integration of LLC into 100 W USB-PD chargers the size of US power plugs. Research designs at 5 MHz with GaN switches reach 98 % efficiency at 500 W; commercial 1 kW server PSUs routinely measure 97 % efficient. The LLC has become to the 2020s what the flyback was to the 1980s — the de facto isolated DC-DC topology of its era.