MOSFET Switching

What a power MOSFET actually is

The full name — metal-oxide-semiconductor field-effect transistor — describes the cross-section. A heavily doped source and drain sit at the ends; between them a thin layer of silicon dioxide (the gate oxide, typically 50–500 Å) sits between the semiconductor and a polysilicon gate electrode. Apply a positive voltage on the gate (for an n-channel device) and the field across the oxide attracts electrons to the silicon surface. When V_GS exceeds the threshold V_th, the surface inverts to n-type and a continuous conducting channel bridges source to drain. Lift V_GS back below V_th and the channel evaporates: the device is off.

Because the gate is electrically isolated by the oxide, no DC current flows into it. You charge the gate capacitance — typically 1–100 nC of total gate charge Q_g — once per switching cycle, and the device stays on without further power draw. This is the defining contrast with a bipolar transistor: a BJT needs continuous base current to hold conduction; a MOSFET needs only a held voltage. That is why MOSFETs scale to hundreds of kilohertz with modest drive losses, while BJTs are pinned to the tens of kilohertz.

The power MOSFET differs from the small-signal MOSFETs inside a CPU mostly by geometry: a vertical structure stacks source over body over a thick lightly-doped n-drift region over the drain on the wafer's underside. That drift region holds off hundreds of volts when the device is off. Trench-gate, planar, and superjunction variants are different ways of packing more current density into the same blocking voltage.

The four parameters that decide everything

Any power-electronics datasheet reduces to four headline numbers. Choose a MOSFET by looking at them in this order.

Parameter	Symbol	Typical range	What it sets
Drain-source breakdown	V_DSS	20 V – 1700 V	Maximum off-state voltage; pick ≥ 1.5× rail
On-resistance	R_DS(on)	0.5 mΩ – 1 Ω	Conduction loss P = I_D² · R_DS(on)
Total gate charge	Q_g	1 – 200 nC	Switching speed; drive-current requirement
Continuous drain current	I_D	1 A – 600 A	Thermally-limited current capacity at T_J = 100 °C

Two derived figures of merit summarise device technology in a single number. R_DS(on) × Q_g (a constant for a given silicon technology — superjunction halved it around 2005) trades conduction against switching loss. R_DS(on) × A (resistance times die area) measures how much current per square millimetre the process can deliver; SiC wins this by ~3× over silicon at 1200 V, GaN by ~10× at 600 V.

Switching losses, the headline cost

An ideal switch dissipates zero power: in the on-state V across it is zero, in the off-state I through it is zero. A real switch spends a brief but finite window with both V and I non-zero — the switching transition. During turn-on the gate charges through the Miller plateau while V_DS collapses and I_D rises; during turn-off the reverse. Integrating the V_DS · I_D product over each transition gives the energy lost per switching event.

E_sw_on  ≈ ½ · V_DS · I_D · t_on
E_sw_off ≈ ½ · V_DS · I_D · t_off
P_sw     = (E_sw_on + E_sw_off) · f_switching

Add this to conduction loss P_cond = D · I_D² · R_DS(on), where D is the on-state duty cycle, and you have the total device dissipation. In a hard-switched silicon converter running at 100 kHz, switching loss typically equals or exceeds conduction loss. Halving t_on (faster gate drive, lower Q_g, or SiC/GaN) directly halves switching losses, which is why every datasheet brags about its rise and fall times.

Worked example: a 5 kW buck converter

Consider a synchronous-buck DC-DC converter, 400 V input, 48 V output, 5 kW load, switching at 100 kHz with a 50%-ish duty cycle. The high-side MOSFET sees V_DS = 400 V in off-state and I_D ≈ 12.5 A during its on-time. Let R_DS(on) = 50 mΩ, t_on + t_off = 40 ns.

Conduction loss  P_cond = D · I_D² · R_DS(on)
                        = 0.12 · 12.5² · 0.050
                        = 0.94 W

Switching loss   P_sw   = ½ · V_DS · I_D · (t_on+t_off) · f_sw
                        = 0.5 · 400 · 12.5 · 40e-9 · 100e3
                        = 10 W

Total            P_tot  ≈ 11 W per device

Conduction is negligible; switching dominates. Drop to a SiC MOSFET with t_on + t_off = 15 ns and switching loss falls to 3.75 W — a 70 % reduction in total dissipation. That is why DC fast chargers and 800 V EV powertrains converted to SiC the moment device cost crossed the breakeven line.

The gate driver — the brain behind the muscle

You cannot drive a power MOSFET directly from a microcontroller GPIO. A 100 nC gate switched in 50 ns demands 2 A peak; a logic pin sources at most 20 mA. The gate driver IC is a dedicated buffer that sits between the controller and the MOSFET, translating a 3.3 V logic command into a 0–12 V (or -5 to +15 V) high-current gate signal. Its responsibilities are:

• Peak source/sink current. 1–10 A typical, set by the required transition time and the gate-charge profile.
• Voltage translation and level shifting. The high-side gate of a half-bridge floats at the switch node; the driver needs a bootstrap capacitor or an isolated supply to keep V_GS in spec.
• Dead-time enforcement. Inserting 50–500 ns gap between high-side and low-side turn-on to prevent shoot-through.
• Miller clamp. A separate low-impedance pull-down active during off, fighting the dV/dt-induced charge injection through C_GD that would otherwise re-trigger the device.
• Protection. Desat detection (current-overload trip in nanoseconds), under-voltage lockout (UVLO), short-circuit response.

Modern integrated half-bridge gate drivers (TI UCC21520, Infineon EiceDRIVER, Analog Devices ADuM4135) package all of this into a 16-pin SOIC with reinforced isolation and propagation delays under 30 ns. For SiC and GaN, dedicated drivers with negative off-bias and tight dV/dt immunity are required — generic Si drivers will false-trigger.

Si, SiC, and GaN — three semiconductors, three regimes

Technology	Voltage range	Switching freq	R_DS(on)·A	Strengths	Where it lives
Si planar / trench	20 – 250 V	≤ 1 MHz	baseline	Cheap, mature, robust body diode	Logic-level loads, automotive 12 V, low-voltage SMPS
Si superjunction	500 – 900 V	≤ 500 kHz	0.3× baseline	Best Si performance, mature ecosystem	PFC stages, server PSUs, induction cooktops
SiC MOSFET	650 – 1700 V (3.3 kV emerging)	50 kHz – 250 kHz	~0.1× baseline	Fast body diode, high T_J (175 °C+), low E_sw	EV traction, DC fast chargers, solar string inverters
GaN HEMT (lateral)	100 – 650 V	500 kHz – 5 MHz	~0.05× baseline at 600 V	Ultra-fast, low Q_g, no body diode (reverse cond instead)	USB-C chargers, 48 V data-centre, LiDAR drivers
GaN HEMT (vertical, emerging)	up to 1200 V	under development	projected lower	Higher current per area than lateral GaN	Research; first products 2026–2027

The wide-bandgap revolution is not about being faster than silicon for its own sake; it is about cutting switching loss enough that converters shrink dramatically. A 22 kW EV onboard charger built with Si IGBTs in 2017 weighed 11 kg; the SiC equivalent in 2024 is under 5 kg with higher efficiency. The same shrink applies to inverters, solar PV, industrial drives, and data-centre power.

The body diode and freewheeling current

A power MOSFET cross-section unavoidably contains a PN junction between the P-body and the N-drift region. That junction acts as an antiparallel diode, conducting when V_DS goes negative. In half-bridge topologies this diode is used deliberately: during dead-time, when both high-side and low-side devices are off but inductor current must continue, the body diode of whichever device is in the current path provides freewheel conduction. As soon as the next channel turns on, the body diode is bypassed by the lower-resistance channel — synchronous rectification.

The downside is reverse-recovery. After conducting forward, a silicon body diode stores minority charge; when V_DS reverses, that stored charge must be cleared as a brief negative current spike. In a fast half-bridge this Q_rr appears as a turn-on current spike on the complementary device, causing extra loss and EMI. Two ways to live with it:

• Slow the transition. Add gate resistance to soften dV/dt — costs switching efficiency.
• Use SiC. SiC body diodes have ~10× less Q_rr than silicon equivalents — clean turn-on, low EMI. This alone is often the deciding factor at 800 V.

GaN HEMTs have no body diode at all; reverse conduction happens through the same channel running backward, with a slightly higher forward drop and zero stored charge. The cleanest reverse-recovery in any power switch.

Inside a 100 kW EV traction inverter

The most visible high-volume application of SiC MOSFETs today is the EV traction inverter. The job: take a 400 V or 800 V DC battery and synthesise three-phase AC at variable voltage and frequency to drive a permanent-magnet synchronous motor. The topology has been settled for decades — three half-bridges in parallel — and the only revolution is the device technology that fills them.

Each half-bridge has a high-side and a low-side switch. That's six switching positions for three-phase. At 100 kW into a 400 V bus, peak phase current is around 250 A; the modern recipe is one 1200 V / 400 A SiC MOSFET module per position. Modules integrate the bare-die MOSFET with a freewheeling diode (or rely on the SiC body diode), thermal substrate, and gate-driver pad in a single insulated package; six modules bolt to a liquid-cooled cold plate. Above each module sits a dedicated gate-driver board with isolated power and isolated PWM signals from the central motor controller.

The motor controller runs space-vector modulation at typically 10–20 kHz: each switching cycle, the six gate commands are recomputed to keep the synthesised three-phase fundamental aligned with the rotor position from a resolver or encoder. Silicon IGBT-based inverters from 2015 ran at 8 kHz; SiC inverters from 2024 routinely run 20 kHz with lower total loss, which lets the motor run quieter, cooler, and at higher base speed. Lucid Air's 800 V powertrain pushes 250 kW continuous per axle through SiC at this density.

Other places MOSFETs switch

• Buck and boost converters. Every laptop charger, phone charger, server PSU, and LED driver is a switched-mode buck or boost using one or two MOSFETs. Switching frequency 100 kHz to 5 MHz depending on technology and density target.
• Three-phase motor drives. Industrial VFDs, e-bikes, drones, robot arms, HVAC compressors — anywhere a permanent-magnet or induction motor needs variable speed.
• Switched-mode power supplies. Flyback, forward, half-bridge, full-bridge, LLC resonant — all topologies are MOSFET (or IGBT) bridges with rectification.
• Battery management. Cell balancers, charge/discharge protection FETs, charger pass elements — typically logic-level 12–60 V MOSFETs with very low R_DS(on).
• Class-D audio amplifiers. A half-bridge of MOSFETs switching at 250 kHz – 1 MHz produces a PWM-encoded audio signal; an LC filter recovers the analog waveform. 90 %+ efficient; every soundbar and Bluetooth speaker uses this.
• Solar string inverters. DC from a series-connected PV string is bucked or boosted, then inverted to three-phase grid AC. SiC has cut inverter loss and size in half over silicon IGBT.
• Wireless charging. Resonant LC tanks driven by half-bridge or full-bridge MOSFETs at 85–360 kHz transfer power across a few-millimetre air gap.
• Solid-state relays and circuit breakers. Two back-to-back MOSFETs replace the contacts of a mechanical relay or breaker; faster, silent, no wear.

Topology patterns

Almost every power-electronics circuit reduces to a handful of MOSFET building blocks.

Building block	Switches	Common uses
Low-side switch	1	Driving a relay coil, fan, LED, brushed DC motor (unidirectional)
High-side switch	1 (+ level shifter)	eFuse, hot-swap, load disconnect
Half-bridge	2 (HS + LS)	Synchronous buck, boost, half of an H-bridge, single-phase Class D
Full bridge / H-bridge	4	Bidirectional brushed-DC drive, full-bridge SMPS, single-phase inverter
Three-phase bridge	6 (3 half-bridges)	BLDC/PMSM motor drive, three-phase inverter, three-phase PFC
Cascode	2 stacked	GaN cascode (Si gate + GaN drift) — enhancement-mode behaviour from depletion device
Synchronous rectifier	1 per output	Replaces forward-conduction diode in low-voltage SMPS, ~1 % efficiency gain

Common pitfalls

• Underspecifying V_DSS. Inductive ringing on a hard-switched 400 V rail can spike to 700 V transiently. A 600 V device will fail; rule of thumb is V_DSS ≥ 1.5× steady-state rail, sometimes 2× with worst-case inductance.
• Ignoring junction temperature derating. Datasheet R_DS(on) is at T_J = 25 °C. At 125 °C it is typically 1.7× higher. Conduction loss design must use the hot value.
• Skimping on the gate driver. A "1 A" gate driver with 100 nF of bootstrap capacitor cannot turn on a 200 nC SiC module in any sensible time. Always size driver peak current to t_target = Q_g / I_drive.
• Forgetting C_oss losses. The output capacitance C_oss × V² / 2 is energy stored in the off-state that dumps on every turn-on (in hard-switched topologies). At 800 V and 1 nF, that is 320 nJ per cycle — 32 W at 100 kHz. Soft-switching topologies (resonant, ZVS) hide this loss but pay an order-of-magnitude in topology complexity.
• dV/dt-induced false turn-on. When one device of a half-bridge turns on hard, the dV/dt across the off device couples through C_GD into the gate and can lift V_GS above V_th, causing momentary shoot-through. Mitigation: low gate-loop inductance, Miller clamp, negative off-bias on SiC (-2 to -5 V).
• Body-diode reverse-recovery surprises. Silicon body diodes have Q_rr from ~1 µC. Switching at 100 kHz this dumps watts of loss and produces 60 MHz EMI. Either slow the gate, add an external Schottky in parallel, or use SiC.
• Layout matters more than the device. Common-source inductance L_s between the source pad and the gate-driver return adds a back-EMF that fights the drive — 5 nH at 5 A/ns is 25 V of error. SiC and GaN packages now route a separate Kelvin source pin specifically to bypass this. Use it.